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f71869e super i/o + hardware monitor release date: dec, 2010 version: v0.21p
finte k feature integration technology inc. dec, 2010 v0.21p 1 f71869e f71869e datasheet revision history version date page revision history 0.10p 2009/09 preliminary version 0.11p 2009/09 106- 108 111 add power saving related register add application circuit 0.12p 2009/09 6 109 110 revise pin configuration change the package to lqfp-128 remove the previous schematic 0.13p 2009/10 - 109 modify gpio6x register typo. update application circuit 0.14p 2009/10 13 18 add description of trapping in fanctl1, 2, 3 revise typo: the default of timing_gpio is timing function add description of trapping in fanctl1, 2, 3 0.15p 2009/10 10 11 12 revise pin 1, 122 description revise pin 2 5 description revise the typo of fanin1 description 0.16p 2009/11 28 35 36 63 110 121 add section 5.2.12 for one fan with multi-temperature description. modify section 5.6 with peci 3.0 description modify section 5.7 with eup timing sequence. add peci 3.0 command and register description modify eup register description update application circuit 0.17p 2009/11 63 modify register description of index 31h/36h/37h. 0.18p 2009/12 48 60 62 64 78 96 111 113 114 117 118 119 124 modify typo of register index 29h bit2 and 2ah bit4 modify case_sts index 03h bit 0 add new tsi mode enable register ? index 07h update configuration register ? index 0ah (bit 1) add ovp option select ? index 3fh (bit 0) update fan mode select register ? index 96h (bit 2-0) auto swap change to default disable from enable. update watchdog timer config. register 1 ? index f5h (bit 1, 0) update eup control register ? index e1h (bit 7-6) update eup control register ? index e2h (bit 7 and 0) update wakeup enable register ? index e8h (bit 4) update pme event status register ? index f3h (bit 3) add led signal invert disable bit ? index f8h (bit 7) update vddok delay register ? index f5h (bit 7,6 & 4,3) update application circuit. delete wdt_en function of pin 122 0.19p 2010/01 45 124 modify typo. of chip id description update pin45 circuit 0.20p 2010/05 81 update register description for fan control 0.21p 2010/12 55, 56 60 10 64 17, 19 50 update rs485 enable register description update ovt register correct pin type add 2d ? 2fh in voltage reading and limit register correct pin description update wakeup control register ? index 2dh bit5 description
finte k feature integration technology inc. dec, 2010 v0.21p 2 f71869e 46 update multi-function select register 1 ? index 28h bit5 description please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applicat these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal in jury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales.
finte k feature integration technology inc. dec, 2010 v0.21p 3 f71869e table of contents 1. general des cription............................................................................................................ ................................ 5 2. feature ........................................................................................................................ .............................................. 6 3. pin config uration.............................................................................................................. .................................... 9 4. pin descri ption ................................................................................................................ ..................................... 10 4.1 p ower p ins ............................................................................................................................... ............................10 4.2 lpc i nterface ............................................................................................................................... ....................... 11 4.3 fdc ............................................................................................................................ ........................................... 11 4.4 uart and sir ............................................................................................................................ ...........................12 4.5 p arallel p ort ............................................................................................................................... .......................14 4.6 h ardware m onitor ............................................................................................................................... ...............15 4.7 acpi f unction p ins ............................................................................................................................... ...............17 4.8 p ower s aving and o thers ............................................................................................................................... ....18 4.9 kbc f unction ............................................................................................................................... ........................19 5. functional description ...................................................................................................... ................................ 20 5.1 p ower t rap o peration ............................................................................................................................... .........20 5.2 h ardware m onitor ............................................................................................................................... ...............20 5.3 acpi f unction ............................................................................................................................... .......................31 5.4 p ower t iming c ontrol s equence .......................................................................................................................33 5.5 st1, st2 and atx_pwrgdsw t iming ................................................................................................................34 5.6 amd tsi and i ntel peci 3.0 f unction .................................................................................................................35 5.7 eup p ower s aving f unction ............................................................................................................................... 36 6. register d escription........................................................................................................... .............................. 40 6.1 g lobal c ontrol r egisters ............................................................................................................................... ..44 6.2 fdc r egisters (cr00) ......................................................................................................................... ...............51 6.3 uart1 r egisters (cr01) ......................................................................................................................... ...........54 6.4 uart2 r egisters (cr02) ......................................................................................................................... ...........55 6.5 p arallel p ort r egister (cr03)......................................................................................................................... .57 6.6 h ardware m onitor r egisters (cr04) ................................................................................................................59 6.7 kbc r egisters (cr05) ......................................................................................................................... ...............96 6.8 gpio r egisters (cr06)......................................................................................................................... ..............97 6.9 w atch d og t imer r egisters (cr07)................................................................................................................. 111
finte k feature integration technology inc. dec, 2010 v0.21p 4 f71869e 6.10 pme, acpi, and eup p ower s aving r egisters (cr0a) ................................................................................ 113 7. electrical characteristic ............................................................................................................................. 121 8. ordering information ............................................................................................................................... ......... 122 9. package dimensions (128-lqfp) ....................................................................................................................... 122 10. application circuit ............................................................................................................................... ............. 124
finte k feature integration technology inc. dec, 2010 v0.21p 5 f71869e 1. general description the f71869e which is the featured io chip for pc system is equi pped with one ieee 1284 parallel port, two uart ports, hardware keyboard controller, sir and one f dc. the f71869e integrates with hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3 temperature sensor pins for the accurate dual current type temperature measurement for cpu thermal diode or external tr ansistors 2n3906. others, the f71869e supports newest amd tsi and intel peci 3.0 interfaces and intel ibex peak smbus fo r temperature sensing and provides the power sequence controller function for amd platform the f71869e provides flexible features for multi-directional application. fo r instance, the f71869e provides 45 gpio pins (multi-pin), irq sharing function also designed in uart feature for particular usage and accurate current mode h/w monitor will be worth in measurement of temper ature, provides 3 modes fan speed control mechanism included manual mode/stage auto mode/linear auto mode for users? selection. a power saving function which is in order to save the curr ent consumption when the system is in the soft off state is also integrated a power saving function. the power savi ng function supports that system boot-on not only by pressing the power button but also by the wake-up event. when the system enters the s4/s5 state, f71869e can cut off the vsb power rail which supplies powe r source to the devices like the lan chip, the chipset, the sio, the audio codec, dram, and etc. the pc system can be simulated to g3-like state when system enters the s4/s5 states. at the g3-like state, the f71869e consumes the 5vsb power rail only. the integrated two control pins are utilized to turn on or off vsb power rail in the g3-like stat us. the turned on vsb rail is supplied to a wake up device to fulfill a low power consumption system which supports a wake up function. these features as above description will help you more and improve produ ct value. finally, the f71869e is powered by 3.3v voltage, with the lpc interf ace in the green package of 128-lqfp (14*14).
finte k feature integration technology inc. dec, 2010 v0.21p 6 f71869e 2. feature ? general functions ? comply with lpc spec. 1.0 ? support dpm (device power management), acpi ? support amd power sequence controller ? provides one fdc, two uarts, hardware kbc and parallel port ? h/w monitor functions ? support amd tsi interface, intel peci interface, intel block read/write smbus interface ? 46 gpio pins for flexible application ? 24/48 mhz clock input ? packaged in 128-lqfp and powered by 3.3vcc ? fdc ? compatible with ibm pc at disk drive systems ? variable write pre-compensation with track selectable capability ? support vertical recording format ? dma enable logic ? 16-byte data fifos ? support floppy disk drives and tape drives ? detects all overrun and under run conditions ? built-in address mark detection circuit to simplify the read electronics ? completely compatible with industry standard 82077 ? 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k, 500k, 1m, 2m bps data transfer rate ? uart ? two high-speed 16c550 compatible uart with 16-byte fifos ? fully programmable serial-interface characteristics ? baud rate up to 115.2k ? support irq sharing ? support ring-in wakeup ? infrared ? support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps
finte k feature integration technology inc. dec, 2010 v0.21p 7 f71869e ? parallel port ? one ps/2 compatible bi-directional parallel port ? support enhanced parallel port (epp) ? compatible with ieee 1284 specification ? support extended capabilities port (ecp) ? compatible with ieee 1284 specification ? enhanced printer port back-drive current protection ? keyboard controller ? lpc interface support serial interrupt channel 1, 12. ? two 16bit programmable address fully decoder, default 0x60 and 0x64. ? support two ps/2 interface, one for ps/2 mouse and the other for keyboard. ? keyboard?s scan code support set1, set2. ? programmable compatibility with the 8042. ? support both interrupt and polling modes. ? fast gate a20 and hardware keyboard reset. ? hardware monitor functions ? 3 dual current type ( 3 ) thermal inputs for cpu thermal diode and 2n3906 transistors ? temperature range -40 ~127 ? 9 sets voltage monitoring (6 external and 3 internal powers) ? voltage monitor supports over voltage protection (ovp) ? high limit signal (pme#) for vcore level ? 3 fan speed monitoring inputs ? 3 fan speed pwm/dc control outputs(support 3 wire and 4 wire fans) ? the fan pwm output frequency can be programmed to 23.5k or 220hz for lcd backlight adjustment ? stage auto mode ( 2-limit and 3-stage)/linear auto mode/manual mode ? issue pme# and ovt# hardware signals output ? case intrusion detection circuit ? watchdog comparison of all monitored values ? power saving controller ? acpi timing and power control ? wake-up supported ? integrate amd tsi interface
finte k feature integration technology inc. dec, 2010 v0.21p 8 f71869e ? integrate intel peci 3.0 spec. ? support amd power sequence controller ? intel block read/write smbus interface ? package ? 128-pin lqfp (14*14) green package
finte k feature integration technology inc. dec, 2010 v0.21p 9 f71869e 3. pin configuration figure1. f71869e pin configuration (14 *14)
finte k feature integration technology inc. dec, 2010 v0.21p 10 f71869e 4. pin description i/o 12t i/o 16t-u47k - ttl level bi-directional pin with 12 ma source-sink cap ability. - ttl level bi-directional pin with 16 ma source-sink cap ability. with internal 47k pull-up. i/ood 12t5v i/od 16t5v - ttl level bi-directional pin, can select to od or out by register, with 12 ma source-sink capability. - ttl level bi-directional pin, open-drain output with 16 ma source-sink capability, 5v tolerance. od 16-5v-u10k i/ood 8st5v i/ood 12st5v i/od 14st5v i lv /o d8-s1 i lv /od 12 o 8t5v-u47k - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 8 ma sink capability, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - ttl level bi-directional pin and schmitt trigger, open-drain output with 14 ma sink capability, 5v tolerance. - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.). output with 8ma drive and 1ma sink capability. - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.). output with 12ma sink capability. - output pin with 8 ma source-sink capability, pull-up 47k ohms, 5v tolerance. o 8 o 12 o 16 - output pin with 8 ma source-sink capability. - output pin with 12 ma source-sink capability. - output pin with 16 ma source-sink capability. aout - output pin(analog). od 12 od 14-5v od 12-5v - open-drain output pin with 12 ma sink capability. - open-drain output pin with 14 ma sink capability, 5v tolerance. - push-pull/open-drain output pin with 12 ma sink capability, 5v tolerance. in t5v in st-u47k - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. with internal pull-up 47k resistor. in st5v - ttl level input pin and schmitt trigger, 5v tolerance. ain - input pin(analog). p - power. 4.1 power pins pin no. pin name type description 4,37 vcc p power supply voltage input with 3.3v (support ovp) 45 5vsb p 5v stand-by power input 68 vsb p stand-by power supply voltage input 3.3v 86 vbat p battery voltage input 88 agnd(d-) p analog gnd 99 vsb p stand-by power supply voltage input 3.3v 20, 48, 73, 117 gnd p digital gnd
finte k feature integration technology inc. dec, 2010 v0.21p 11 f71869e 4.2 lpc interface pin no. pin name type pwr description 29 lreset# in st5v vcc reset signal. it can connect to pcirst# signal on the host. 30 ldrq# o 16 vcc encoded dma request signal. 31 serirq i/o 16t-u47k vcc serial irq input/output. 32 lfram# in st-u47k vcc indicates start of a new cycle or termination of a broken cycle. 33-36 lad[0:3] i/o 16t-u47k vcc these signal lines communicat e address, control, and data information over the lpc bus between a host and a peripheral. 38 pciclk in st vcc 33mhz pci clock input. 39 clkin in st vcc system clock input. according to the input frequency 24/48mhz. 4.3 fdc pin no. pin name type pwr description gpio30 i/od 14st5v default general purpose io. 7 densel# od 14-5v vcc drive density select. set to 1 - high data rate.(500kbps, 1mbps) set to 0 ? low data rate. (250kbps, 300kbps) fdc function is selected by register setting. gpio31 i/od 14st5v default general purpose io. 8 moa# od 14-5v vcc motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. fdc function is selected by register setting. gpio32 i/od 14st5v default general purpose io. 9 drva# od 14-5v vcc drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. fdc function is selected by register setting. gpio33 i/od 14st5v default general purpose io. 10 wdata# od 14-5v vcc write data. this logic low open drain writes pre-compensation serial data to the selected fdd. an open drain output. fdc function is selected by register setting. gpio34 i/od 14st5v default general purpose io. 11 dir# od 14-5v vcc direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion fdc function is selected by register setting. 12 gpio35 i/od 14st5v vcc default general purpose io.
finte k feature integration technology inc. dec, 2010 v0.21p 12 f71869e step# od 14-5v step output pulses. this active low open drain output produces a pulse to move the head to another track. fdc function is selected by register setting. gpio36 i/od 14st5v default general purpose io. 13 hdsel# od 14-5v vcc head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 fdc function is selected by register setting. gpio37 i/od 14st5v default general purpose io. 14 wgate# od 14-5v vcc write enable. an open drain output. fdc function is selected by register setting. gpio50 i/ood 12st5v default general purpose io. 15 rdata# in st5v vcc the read data input signal from the fdd. fdc function is selected by register setting. gpio51 i/ood 12st5v default general purpose io. 16 trk0# in st5v vcc track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. fdc function is selected by register setting. gpio52 i/ood 12st5v default general purpose io. 17 index# in st5v vcc this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. fdc function is selected by register setting. gpio53 i/ood 12st5v default general purpose io. 18 wpt# in st5v vcc write protected. this active lo w schmitt input from the disk drive indicates that the disk ette is write-protected. fdc function is selected by register setting. gpio54 i/ood 12st5v default general purpose io. 19 dskchg# in st5v vcc diskette change. this signal is active low at power on and whenever the diskette is removed. fdc function is selected by register setting. 4.4 uart and sir pin no. pin name type pwr description gpio42 i/ood 12t5v default general purpose io. 27 irtx o 12 vcc infrared transmitter output. t he function is selected by register setting. gpio43 i/ood 12t5v default general purpose io. 28 irrx in st5v vcc infrared receiver input. the function is selected by register
finte k feature integration technology inc. dec, 2010 v0.21p 13 f71869e setting. 118 dcd1# in st5v vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. 119 ri1# in st5v vsb ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 120 cts1# in st5v vcc clear to send is the modem control input. dtr1# o 8t5v-u47k uart 1 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. internal 47k ohms pulled high and disable after power on strapping. 121 fan40_100 in t5v vcc power on strapping pin: 1(default): (internal pull high) power on fan speed default duty is 40%.(pwm) 0: (external pull down) power on fan speed default duty is 100%.(pwm) 122 rts1# o 8t5v-u47k vcc uart 1 request to send. an active low signal informs the modem or data set that the controller is ready to send data. 123 dsr1# in st5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. sout1 o 8t5v-u47k uart 1 serial output. used to tr ansmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. 124 config4e_2e in t5v vcc power on strapping: 1(default): configuration register 4e 0: configuration register 2e 125 sin1 in st5v vcc serial input. used to receive serial data through the communication link. gpio20 i/ood 8st5v default general purpose io. 126 dcd2# in st5v vcc data carrier detect. an acti ve low signal indicates the modem or data set has detected a data carrier. the function is selected by register setting. gpio21 i/ood 8st5v default general purpose io. 127 ri2# in st5v vsb ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. the function is selected by register setting. gpio22 i/ood 8st5v default general purpose io. 128 cts2# in st5v vcc clear to send is the modem control input. the function is selected by register setting. gpio23 i/ood 8st5v default general purpose io. 1 dtr2# o 8t5v-u47k vcc u a rt 2 data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. the function is selected by register setting. 2 gpio24 i/ood 8st5v vcc default general purpose io.
finte k feature integration technology inc. dec, 2010 v0.21p 14 f71869e rts2# o 8t5v-u47k .uart 2 request to send. an active low signal informs the modem or data set that the controller is ready to send data. the function is selected by register setting. gpio25 i/ood 8st5v default general purpose io. 3 dsr2# in st5v vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. the function is selected by register setting. gpio26 i/ood 8st5v default general purpose io. 5 sout2 o 8t5v-u47k vcc uart 2 serial output. used to tr ansmit serial data out to the communication link. the function is selected by register setting. gpio27 i/ood 8st5v default general purpose io. 6 sin2 in st5v vcc serial input. used to receive serial data through the communication link. the function is selected by register setting. 4.5 parallel port pin no. pin name type pwr description 100 slct in st5v vcc an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 101 pe in st5v vcc an active high input on this pin indicates that the printer has detected the end of the paper. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 102 busy in st5v vcc an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. 103 ack# in st5v vcc an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 104 slin# i/ood 12st5v vcc output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 105 init# i/ood 12st5v vcc output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 106 err# in st5v vcc an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode.
finte k feature integration technology inc. dec, 2010 v0.21p 15 f71869e 107 afd# i/ood 12st5v vcc an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 108 stb# i/ood 12st5v vcc an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 109 pd0 i/o 12st5v vcc parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. 110 pd1 i/o 12st5v vcc parallel port data bus bit 1. 111 pd2 i/o 12st5v vcc parallel port data bus bit 2. 112 pd3 i/o 12st5v vcc parallel port data bus bit 3. 113 pd4 i/o 12st5v vcc parallel port data bus bit 4. 114 pd5 i/o 12st5v vcc parallel port data bus bit 5. 115 pd6 i/o 12st5v vcc parallel port data bus bit 6. 116 pd7 i/o 12st5v vcc parallel port data bus bit 7. 4.6 hardware monitor pin no. pin name type pwr description 93 vin6 ain vdda voltage input 6. this pin support ovp function, and default is disable. 94 vin5 ain vdda voltage input 5. this pin support ovp function, and default is disable. 95 vin4 (vdimm) ain vdda voltage input 4 or vdimm input used in amd platform. the input voltage level for timing control usage must be over 1v after voltage divider. 96 vin3 (vdda) ain vdda voltage input 3 or vdda input used in amd platform. the input voltage level for timing control usage must be over 1v after voltage divider. 97 vin2 (vldt) ain vdda voltage input 2 or vldt input used in amd platform. the input voltage level for timing control usage must be over 1v after voltage divider. 98 vin1 (vcore) ain vdda voltage input for vcore. the input voltage level for timing control usage must be over 0.7v. 21 fanin1 in st5v vcc fan 1 tachometer input. 22 fanctl1 ood 12-5v aout vcc fan 1 control output. it is also a trap pin to select a pwm or a dac output, except being an output pin. it defaults to be a voltage output by pulling down inte rnally. it is set as a pwm output as connected a 4.7k resistor and pulled high to 3.3v. the pwm output frequency can be programmed to 220hz for lcd backlight control. 23 fanin2 in st5v vcc fan 2 tachometer input.
finte k feature integration technology inc. dec, 2010 v0.21p 16 f71869e 24 fanctl2 ood 12-5v aout vcc fan 2 control output. it is also a trap pin to select a pwm or a dac output, except being an output pin. it defaults to be a voltage output by pulling down inte rnally. it is set as a pwm output as connected a 4.7k resistor and pulled high to 3.3v. the pwm output frequency can be programmed to 220hz for lcd backlight control. gpio40 i/ood 12st5v default general purpose io. 25 fanin3 in st5v vcc fan 3 speed input. this function is selected by register setting. gpio41 i/ood 12st5v default general purpose io. this pin default function is gpio function. please take care the application if user wants to implement fanctl function. 26 fanctl3 ood 12-5v aout vcc fan 3 control output. it is also a trap pin to select a pwm or a dac output, except being an output pin. it defaults to be a voltage output by pulling down internally. it is set as a pwm output as connected a 4.7k resistor and pulled high to 3.3v. the pwm output frequency can be programmed to 220hz for lcd backlight control. peci_req# od 12 peci request signal. selected by timing_gpio trap pin. tsi_clk i/od 125v amd tsi interface clock output. selected by timing_gpio trap pin. 57 ibx_scl od 12 vsb intel ibex peak platform hardw are monitor interface clock output. selected by register. peci i lv /o d8-s1 intel peci hardware monitor interface. when timing_gpio pin is set in gpio function (i ntel mode). peci function can be set by the register. tsi_dat i lv /od 12 amd tsi interface data input. when timing_gpio pin is set in timing function (amd mode). tsi function can be set by the register. 58 ibx_sda i lv /od 12 vsb intel ibex peak platform hardw are monitor interface input. when timing_gpio pin is set in gpio function (intel mode). ibx function can be set by the register. wdtrst# od 12-5v watch dog timer signal output. 63 gpio14 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting 67 ovt# od 12-5v vsb over temperature signal output. 79 pme# od 12-5v-u47k vsb generated pme event. it supports the pci pme# interface. this signal allows the peripheral to request the system to wake up from the s3 state. 89 d3+(system) ain vdda thermal diode/transistor temperature sensor input for system use. 90 d2+ ain vdda thermal diode/transistor temperature sensor input. 91 d1+(cpu) ain vdda cpu thermal diode/transistor temperature sensor input. this pin is for cpu use. 92 vref aout vdda voltage sensor output.
finte k feature integration technology inc. dec, 2010 v0.21p 17 f71869e 4.7 acpi function pins pin no. pin name type pwr description gpio10 i/ood 12st5v default general purpose io. gpio function is selected by register setting pci_rst4# o 12-5v it is an output buffer of lreset#. this function is selected by register setting. 59 ibx_scl i/od 125v vsb intel ibex peak platform hardw are monitor interface clock output. this function is selected by register setting. gpio11 i/ood 12st5 default general purpose io. pci_rst5# o 12-5v it is an output buffer of lreset#. this function is selected by register setting. 60 ibx_sda i/od 125v vsb intel ibex peak platform hardw are monitor interface input. this function is selected by register setting. gpio12 i/ood 12st5v default general purpose io. rstcon# in st5v reset button input. this function is selected by register setting. 61 fanctl1 ood 12-5v aout vsb fan 1 control output. this pin provides pwm duty-cycle output or a voltage output. this function is selected by register setting. gpio15 i/ood 12st5v default general purpose io. led_vsb od 12-5v power led for vsb. this functi on is selected by register setting. 64 alert# od 12-5v vsb alert a signal when temperature over limit setting. this function is selected by register setting. gpio16 i/ood 12st5v default general purpose io. 65 led_vcc od 12-5v vsb power led for vcc. this func tion is selected by register setting. cpu_pwrgd od 12-5v cpu power good signal output (detected by vin1~vin4 level good) 66 gpio17 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting 74 pcirst1# od 12-5v vsb it is an output buffer of lreset#. 75 pcirst2# o 12-5v vsb it is an output buffer of lreset#. 76 pcirst3# o 12-5v vsb it is an output buffer of lreset#. 77 s5# in st5v-u47k vsb s5# signal input. atxpg_in in st5v atx power good input. 78 gpio44 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting. pwsin# in ts5v main power switch button input. 80 gpio45 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting. pwsout# od 12-5v-u47k panel switch output. this pin is low active and pulse output. it is power on request output#. 81 gpio46 i/ood 12st5v vsb general purpose io. gpio function is selected by register
finte k feature integration technology inc. dec, 2010 v0.21p 18 f71869e setting. 82 s3# in st5v-u47k vsb s3# input is main power on-off switch input. ps_on# od 12-5v power supply on-off control output. connect to atx power supply ps_on# signal. 83 gpio47 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting. 84 pwok od 12-5v vbat pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. 85 rsmrst# od 12-5v-u10k vbat resume reset# function, it is power good signal of vsb, which rises delayed 66ms as vsb arrives at 2.8v and falls as vsb drops to 2.6v. there is an option to set rsmrst# rises at 3.05v and falls at 2.95v. 87 copen# in st5v vbat case open detection #. this pin is connected to a specially designed low power cmos flip-f lop backed by the battery for case open state preservation during power loss. 4.8 power saving and others pin no. pin name type pwr description 42 event_in# in ts5v vsb wake-up event input. the signal input wakes the system up from the sleep state. 43 ctrl0# od 12 vsb standby power rail control pin 0. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. 44 ctrl1# od 12 vsb standby power rail control pin 1. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. timing_3 od 12-5v active high. timing sequence 3 of power on/off sequence pins. the external pull high resistor is required. (detected by vin3 level good) 46 gpio00 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting timing_4 od 12-5v active high. timing sequence 4 of power on/off sequence pins. the external pull high resistor is required. (detected by vin1 level good) 47 gpio01 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting 49-51 gpio[63:65] i/ood 12t vsb general purpose io. gpio function is selected by register setting 52 timing_gpio in st5v-u47k vsb this pin is timing sequence or gpio trap pin to set function of pin 46, 47, 53, 54. it is defaulted to the timing function by connecting a 47k resistor and pulling high to 3.3v internally. it will be set as gpio function if this pin is connected to ground. 53 timing_2 od 12-5v vsb active high. timing sequence 2 of power on/off sequence pins. the external pull high resistor is required.
finte k feature integration technology inc. dec, 2010 v0.21p 19 f71869e (detected by vin4 level good) gpio02 i/ood 12st5v general purpose io. gpio function is selected by register setting timing_1 od 12-5v active high. timing sequence 1 of power on/off sequence pins. the external pull high resistor is required. (output detected by vccok(vddo k) level good, ref figure 14 ) 54 gpio03 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting st2 od 12 status pin2 for s0#/s3#/s5# states application. (default function) in s0# ? st2 pin status is tri-state. in s3# ? st2 pin status is low level. in s5# ? st2 pin status is tri-state, and can be programmed low level. slotocc# in st5v cpu slotocc# input. 55 gpio04 od 12-5v vsb general purpose io. gpio function is selected by register setting st1 od 12 status pin1 for s0#/s3#/s5# st ates application. (default function) in s0# ? st1 pin status is tri-state. in s3# ? st1 pin status is low level. in s5# ? st1 pin status is tri-state. 56 gpio05 i/ood 12st5v vsb general purpose io. gpio function is selected by register setting atx_ pwrgdsw od 24-5v atx_pwrgdsw for s0#/s3#/s 5# states application. in s0# ? atx_pwrgdsw pin status is low-state. in s3# ? atx_pwrgdsw pin status is tri-state. in s5# ? atx_pwrgdsw pin status is tri-state, and can be programmed low-state. gpio13 i/ood 24st5v general purpose io. gpio function is selected by register setting 62 beep od 24-5v vsb beep pin. 4.9 kbc function pin no. pin name type pwr description 40 kbrst# od 16-5v-u10k vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) 41 ga20 od 16-5v-u10k vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) 69 kdata i/od 16st5v vsb keyboard data. 70 kclk i/od 16st5v vsb keyboard clock. 71 mdata i/od 16st5v vsb ps2 mouse data. 72 mclk i/od 16st5v vsb ps2 mouse clock.
finte k feature integration technology inc. dec, 2010 v0.21p 20 f71869e 5. functional description 5.1 power trap operation the f71869e provides four pins for power on hardware strapping to select functions. there is a form to describe how to set the functions you want. table1. power on trap configuration pin no. symbol value description 1 set pin 46, 47, 53, 54 as timing sequence output (default) 52 timing_gpio 0 set pin 46, 47, 53, 54 as gpio 1 power on fan speed default duty is 40% (pwm) (default) 121 fan40_100 0 power on fan speed default duty is 100%(pwm) 1 configuration register i/o port is 4e/4f. (default) 124 config4e_2e 0 configuration register i/o port is 2e/2f. 1 fanctrl1 is pwm mode. connect a 4.7k resistor and pull high to 3.3v. 22 fanctl1 0 fanctlr1 is dac mode. (default) 1 fanctrl2 is pwm mode. connect a 4.7k resistor and pull high to 3.3v. 24 fanctl2 0 fanctlr2 is dac mode. (default) 1 fanctrl3 is pwm mode. connect a 4.7k resistor and pull high to 3.3v. 26 fanctl3 0 fanctlr3 is dac mode. (default) 5.2 hardware monitor for the 8-bit adc has the 8mv lsb, the maximum input voltage of the analog pin is 2.048v. therefore the voltage under 2.048v (ex: 1.5v) can be directly connected to these analog inputs. the voltage higher than 2.048v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc/vsb/vbat is an excepti on for it is main power of the f71869e. therefore 3vcc/vsb/vbat can directly connect to this chip?s power pin and need no external resistors. there are two functions in this pin with 3.3v. the first function is to supply internal analog power of the f71869e and the second function is that voltage with 3.3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial resistors are two 150k ohm, so that the internal reduced voltage is half of +3.3v. there are four voltage inputs in the f71869e and the voltage divided formula is shown as follows:
finte k feature integration technology inc. dec, 2010 v0.21p 21 f71869e 2 1 2 v 12 r r r v vin + = + where v +12v is the analog input voltage, for example. if we choose r1=27k, r2=5.1k, the exact input voltage for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows. vin (lower than 2.048v) 8-bit adc with 8 mv lsb voltage inputs r1 r2 vin1(max2.048v) vin(higher than 2.048v) (directly connect to the chip) 3vcc/vsb (directly connect to the chip) vin3.3 150k 150k typical thermister connection r thm 10k, 25 c r vref 10k, 1% 2n3906 typical bjt connection d+ d- figure 2. hardware monitor configuration the f71869e monitors three remote temperature s ensors. these sensors can be measured from -40c to 127c. more detail please refer register description. table 3. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906
finte k feature integration technology inc. dec, 2010 v0.21p 22 f71869e 5.2.1 table range: table 4. display range is from -40c to 127c in 2?s complement format. temperature digital output -40c 1101 1000 -1c 1111 1111 1c 0000 0001 90c 0101 1010 127c 0111 1111 open 1000 0000 5.2.2 monitor temperature from ?thermistor? the f71869e can connect three thermistors to m easure environment temperature or remote temperature. the specification of thermistor should be considered to (1) value is 3435k (2) resistor value is 10k ohm at 25 c. in the figure 2, the thermistor is connected by a serial resistor with 10k ohm, then being connected to vref. 5.2.3 monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits pr ovide thermal diode for temperature measurement, the f71869e is capable to these situations. the build-in reference table is for pnp 2n3906 transistor. in the figure 2, the transistor is directly connected into temperature pins. 5.2.4 adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; therefore, careful pcb board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. high frequency emi is best filtered at d+ and d- with an external 2200pf capacitor. too high capacitance may introduce errors due to the rise time of the switched current source. nearly all noise sources tested cause the adc measurement to be higher than the actual temperature, depending on the frequency and amplitude. 5.2.5 monitor temperature from ?smbus device? f71869e provides smbus block read/write compatib le platform control hub (pch) ec smbus protocol, and provides byte read/write protoc ol to read cpu and chipset thermal temperature information. for byte read /write protocol, f71869e supports 4-suit device address to read or write from device information. for block read/write, f71869e support 1 suits device address and maximum
finte k feature integration technology inc. dec, 2010 v0.21p 23 f71869e 17 byte count for read protocol to read from device in formation, and 4 byte count for write protocol to write information to device. 5.2.6 monitor temperature from ?peci? f71869e support intel peci1.1/peci3.0/peci_request/peci_available interfaces to read temperature from peci device. 5.2.7 temperature ovt# signal there is a mode of temperature (t1 to t4) ovt function, and refer t1 to t4 temperature in the below figure. over temperature event will trigger ovt# that shown as figure 3. in hysteresis mode, when monitored temperature exceeds the high temperatur e threshold value, ovt# will be asserted until the temperature goes below the hysteresis temperature. t hyst t ovt# high t1 t2 t3 t4 figure 3 5.2.8 temperature pme# pme# interrupt for temperature is shown as figure 4. temperature exceeding high limit (low limit) or going below high hysteresis (low hyst eresis) will cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register.
finte k feature integration technology inc. dec, 2010 v0.21p 24 f71869e *interrupt reset when interrupt status registers are written 1 pme# (pulse mode) * * t high t hhys * * figure 4 hysteresis mode illustration 5.2.9 fan speed count inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer outputs are over the 5v, the ex ternal trimming circuit should be added to reduce the voltage to obtain the input specification. determine the fan counter according to: rpm 10 5 . 1 count 6 = in other words, the fan speed counter has been read from register, the fan speed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachometer output per round. count 10 5 . 1 rpm 6 = as the register description of datasheet, the parameter ?count? register provides 12-bit resolution for rpm counting. in fintek design, the value of parameter ?count? is from 4096 ~ 64 (5 bit filter). therefore the rpm measure capability is from 366 ~ 23438 rpm. above example is for 2 pulses tachometer (nor mal 4 phases fan) output per round. if you use 8 phases fan, means output 4 pulses per round. the rpm measure capability is from 183 ~ 11719 rpm. 5.2.10 fan speed control the f71869e provides 2 fan speed control methods: one is dac fan control and the other is pwm
finte k feature integration technology inc. dec, 2010 v0.21p 25 f71869e duty cycle. 1. dac fan control the range of dc output is 0~3.3v, controlled by 8-bit register. 1 lsb is about 0.013v. the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 255 value register 8bit programmed 3 . 3 (v) tage output_vol = and the suggested application circuit for dac fan control would be: fanin monitor dc output voltage +12v r10k 1 2 3 jp1 con3 r 10k r 3.6k d1 1n4148 3 2 1 8 4 + - u1a lm358 r27k r 4.7k c 47u q1 pmos c 0.1u r 4.7k figure 5 dac fan control application circuit 2. pwm duty fan control the duty cycle of pwm can be programmed by a 8-bit register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transisto r c + - d s g figure 6 +12/5v pwm fan control application circuit
finte k feature integration technology inc. dec, 2010 v0.21p 26 f71869e 5.2.11 fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode 3. linear auto mode. more detail, please refer the description of registers. each fan can be controlled by up to 8 kinds of temperature input. (1)d1+ temperature (2)d2+ temperature (3) d3+ temperature (4) peci temperature (5) 4 suits smbus master temperature. please refer below structure diagram. after the t0 ~t7 setting ready, select s1 ~ s4 temperature machine from t0 ~ t7, these 4-set temperature data are for maximum temperature comparison. figure 7 relative temperature fan control 1. manual mode for manual mode, it generally acts as software fan speed control. 2. stage auto mode at this mode, the f71869e provides automatic fan s peed control related to temperature variation of expect speed1 expect speed 2 fan1 fan2 d2+ t (t2) d1+ t (t1) peci d3+ t (t2) ibx byte1 ibx byte3:2 ibx byte4 ibx byte5 expect speed 3 fan3
finte k feature integration technology inc. dec, 2010 v0.21p 27 f71869e cpu/gpu or the system. the f71869e can provide tw o temperature boundaries and three intervals, and each interval has its related fan speed pwm duty. all these values should be set by bios first. take below figure as example. when temperature boundaries are set as 45 and 75 c and there are three intervals. the related desired fan speed for every interval is 40%, 80% and 100% (fixed). when the temperature is within 45~75?c, the fan speed will follow 80% pwm duty and that define in registers. it can be said that the fan will be turned on with a specific speed set by bios and automatically controlled with the temperature variation. the f71869e will take charge of all the fan speed control without software support. pwm duty 40% 75 degree c 45 degree c temperature 80% 100% temperature fan speed figure 8 stage mode fan control illustration-1 below is a sample for stage auto mode: set temperature as 60c, 40c and duty as 100%, 70%, 50% 100% 70% 50% 60 degree c 40 degree c bcd temp. fan speed pwm duty hysteresis 57 degree c a figure 9 stage mode fan control illustration-2 a. once temp. is under 40 c, the lowest fan speed keeps 50% pwm duty b. once temp. is over 40 c,60 c, the fan speed will vary from 70% to 100% pwm duty and increase with temperature c. once temp. keeps in 55 c, fan speed keeps in 70% pwm duty d. if set the hysteresis as 3 c (default 4 c), once temp reduces under 57 c, fan speed reduces to 70% pwm duty and stays there.
finte k feature integration technology inc. dec, 2010 v0.21p 28 f71869e 3. linear auto mode otherwise, f71869e supports linear auto mode. below has an example to describe this mode. more detail, please refer the register description. set temperature as 70 c, 40 c and duty as 100%, 70%, 40% 100% 70% 40% 70 degree c 40 degree c ab c d hysteresis 65 degree c temp. fan speed pwm duty figure 10 linear mode fan control illustration a. once temp. is under 40 c, the lowest fan speed keeps 40% pwm duty b. once temp. is over 40 c and under 70 c, the fan speed will vary from 40% to 70% pwm duty and linearly increase with temp. variation. the temp.-fan speed monitoring and flash interval is 1sec. c. once temp. goes over 70 c, fan speed will directly increase to 100% pwm duty (full speed) d. if set the hysteresis as 5 c (default is 4 c), once temp reduces under 65 c (not 70 c), fan speed reduces from 100% pwm duty and decrease linearly with temp..
finte k feature integration technology inc. dec, 2010 v0.21p 29 f71869e 5.2.12 fan speed control with multi-temperature. f71869e supports multi-temperature for one fan control. this function works with linear auto mode can extend two linear slopes for one fan control. as below graph shows, this machine can support more silence fan control in low temperature and high fan speed in high temperature segment. more detail setting please refers the registers.
finte k feature integration technology inc. dec, 2010 v0.21p 30 f71869e 5.2.13 fan_fault# fan_fault# will be asserted when the fan speed doesn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there are two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan speed count can?t reach the fan expected count in time. fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% figure 11 fan_fault# event (2). after the period of detecting fan full speed, pwm_duty > min. duty, fan count is still in 0xfff.
finte k feature integration technology inc. dec, 2010 v0.21p 31 f71869e 5.3 acpi function the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primary concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect different power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one register will keep the status of before power loss. if it is power on before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v
finte k feature integration technology inc. dec, 2010 v0.21p 32 f71869e figure 12 default timing: always off vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v figure 13 optional timing: always on pci reset and pwrok signals the f71869e supports 5 output buffers for 5 reset signals. so far as the pwrok issue is as the figure above. pwrok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed by register. an additional delay could be added to pwrok (0ms, 100ms, 200ms and 400ms). if rs tcion# and pcirst4#/pcirst5# are enabled, rstcon# could be programmed to be asserted via pwrok or pcirst4#/pcirst5#. delay +3.3v atxpg lreset# pcirst1~5# pwrok buffer
finte k feature integration technology inc. dec, 2010 v0.21p 33 f71869e 5.4 power timing control sequence the f71869e offers 4 timing pins which are designed for amd platform power sequence control including vdimm, vdda, vcore, and vldt (default) or other timing application purposes. all the timings on/off are relative to s3#/s5# and can be programmed by the register 0x0af7. as shown in the below figure, the default timings of timing_1~4 are displayed in blue lines, and all the timings are enabled in the s0 state except timing_1. however, timing_2~4 can be programmed to enable in the s3 state, and timing_1 can also be programmed to disable in the s3 state, like the dotted blue line shown in the figure below. vddok_d400 is the pwrok delay timing from vdd3vok. the default setting is that delay 400ms, there are 100ms, 200ms, and 300ms for option. it can be set in the register 0x0af5. figure 14 timing on/off sequence s5 s3 s0 s5 s5# s3# pson# atxpwgd timing_1 timing_2 timing_3 timing_4 cpu_pwrgd vddok_d400 s0 s3
finte k feature integration technology inc. dec, 2010 v0.21p 34 f71869e 5.5 st1, st2 and atx_pwrgdsw timing the f71869e provides three additional timing switching pins which are named as st1, st2 and atxpwrgdsw. they can be applied in the certain applications about power switch which depends on the acpi states. the detail timing can be referred in the following diagrams. the default timing of atx_pwrgdsw in the s5 state is low, but it can be programmed high by the register 0x0af6. s5# s3# pson# vdd3v vddok vddok_d400 atxpg pwrok atx_pwrgdsw 400ms could be programmed low s5 st1 could be programmed low st2 10us 10us s0 s3 figure 15 timing chart of s5->s0->s3
finte k feature integration technology inc. dec, 2010 v0.21p 35 f71869e s5# s3# pson# vdd3v vddok vddok_d400 atxpg pwrok atx_pwrgdsw 400ms s3 st1 st2 10us 10us s0 s5 could be programmed low figure 16 timing chart of s3->s0->s5 5.6 amd tsi and intel peci 3.0 function the f71869e provides intel peci/amd tsi interfaces for new generational cpu temperature sensing. in amdsi interface, there are sic and sid signals for temperature information reading from amd cpu. the sic signal is for clocking use, the other is for data transferring. more details, please refer register description. tsi_clk vddio f71869e amd cpu tsi_clk tsi_dat 300 300 tsi_dat figure 17 amd tsi typical application
finte k feature integration technology inc. dec, 2010 v0.21p 36 f71869e in intel peci interface, the f71869e can connect to cpu directly. the f71869e can read the temperature data from cpu, than the fan control machine of f71869e can implement the fan to cool down cpu temperature. the application circuit is as below. peci f71869e cpu peci intel 100k avoid pre-bios floating figure 18 intel peci typical application in intel peci 3.0 spec., it?s including below commands. the f71869e integrated most of those commands for future advantage application. more detail, please refer the register descriptions. f71869e support peci 3.0 command name peci 1.0 command name status v ping( ) ping( ) v gettemp( ) gettemp( ) v getdib( ) v rdiamsr( ) - wriamsr( ) - rdpciconfiglocal( ) not available in mobile/dt - wrpciconfiglocal( ) not available in mobile/dt - rdpciconfig( ) not available in mobile/dt - wrpciconfig( ) not available in mobile/dt v rdpkgconfig( ) v wrpkgconfig( ) 5.7 eup power saving function the two pins, ctrl0# and ctrl1#, which control the standby power rail on/off to fulfill the purpose which decreases the power consumption when the system in the sleep state or the soft-off state. these two pins connected to the external pmoss and the defaults are high in the sleep state in order to cut off all the standby power rails to save the power consumption. if the system needs to support wake-up function, the two pins can be programmable to set which power rail is turned on. the programmable register is powered by battery. so, the setting is kept even the ac power is lost when the register is set. at the power saving state (fintek calls it g3-like state), the f71869e consumes 5vsb power rail only to realize a low power consumption system. below is eup function?s timing graphs.
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finte k feature integration technology inc. dec, 2010 v0.21p 40 f71869e 6. register description the configuration register is used to control the behavior of the corresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the sout1 pin to change the default value to 0x2e/0x2f. to enable configuration, the entry key 0x87 must be written to the index port. to disable configuration, write exit key 0xaa to the index port. following is a example to enable configuration and disable configuration by using debug. -o 4e 87 -o 4e 87 (enable configuration) -o 4e aa (disable configuration) the following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of all registers and their default value. please refer each device chapter if you want more detail information. global control registers ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register - - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 1 0 0 0 0 1 0 0 0 21 chip id register 2 0 0 0 1 0 1 0 0 23 vendor id register 1 0 0 0 1 1 0 0 1 24 vendor id register 2 0 0 1 1 0 1 0 0 26 uart irq sharing register 0 - - - - 0 0 0 27 configuration port select register - - - 1/0 - - 1/0 1/0 28 multi-function select register1 - - 1 1 1 0 - - 29 multi-function select register2 0 1 1 0 1 1 1 1 2a multi-function select register3 0 0 0 0 0 1 1 1 2b multi-function select register4 0 0 0 0 1 1 1 1 2d wakeup control register 0 0 1 0 1 0 0 0
finte k feature integration technology inc. dec, 2010 v0.21p 41 f71869e device configuration registers ?-? reserved or tri-state fdc device configuration registers (ldn cr00) register 0x[hex] register name default value msb lsb 30 fdc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 0 0 0 0 70 irq channel select register - - - - 0 1 1 0 74 dma channel select register - - - - - 0 1 0 f0 fdd mode register 0 - - 0 1 1 1 0 f2 fdd drive type register - - - - - - 1 1 f4 fdd selection register - - - 0 0 - 0 0 uart1 device configuration registers (ldn cr01) register 0x[hex] register name default value msb lsb 30 uart1 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 rs485 enable register - - 0 0 - - - - uart2 device configuration registers (ldn cr02) register 0x[hex] register name default value msb lsb 30 uart2 device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 0 1 1 f0 rs485 enable register - - - 0 0 0 - - f1 sir mode control register - - 0 0 0 1 0 0 parallel port device configuration registers (ldn cr03) register 0x[hex] register name default value msb lsb 30 parallel port device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1
finte k feature integration technology inc. dec, 2010 v0.21p 42 f71869e 61 base address low register 0 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 1 1 74 dma channel select register - - - 0 - 0 1 1 f0 prt mode select register 0 1 0 0 0 0 1 0 hardware monitor device configuration registers (ldn cr04) register 0x[hex] register name default value msb lsb 30 h/w monitor device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 kbc device configuration registers (ldn cr05) register 0x[hex] register name default value msb lsb 30 kbc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 kb irq channel select register - - - - 0 0 0 1 72 mouse irq channel select register - - - - 1 1 0 0 f0 clock select register 1 0 - - - - 1 1 fe swap register 1 - - 0 0 0 0 1 ff user wakeup code register 0 0 1 0 1 0 0 1 gpio device configuration registers (ldn cr06) register 0x[hex] register name default value msb lsb 30 gpio device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 gpirq channel select register - - - - 0 0 0 0 f0 gpio output enable register - - 0 0 0 0 0 0 f1 gpio output data register - - 1 1 1 1 1 1 f2 gpio pin status register - - - - - - - - f3 gpio drive enable register - - 0 0 0 0 0 0 e0 gpio1 output enable register 0 0 0 0 0 0 0 0 e1 gpio1 output data register 1 1 1 1 1 1 1 1
finte k feature integration technology inc. dec, 2010 v0.21p 43 f71869e e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register 0 0 0 0 0 0 0 0 e4 gpio1 pme enable register 0 0 0 0 0 0 0 0 e5 gpio1 detect edge select register 0 0 0 0 0 0 0 0 e6 gpio1 pme status register 0 0 0 0 0 0 0 0 d0 gpio2 output enable register 0 0 0 0 0 0 0 0 d1 gpio2 output data register 1 1 1 1 1 1 1 1 d2 gpio2 pin status register - - - - - - - - d3 gpio2 drive enable register 0 0 0 0 0 0 0 0 c0 gpio3 output enable register 0 0 0 0 0 0 0 0 c1 gpio3 output data register 1 1 1 1 1 1 1 1 c2 gpio3 pin status register - - - - - - - - b0 gpio4 output enable register - - - - 0 0 0 0 b1 gpio4 output data register - - - - 1 1 1 1 b2 gpio4 pin status register - - - - - - - - b3 gpio4 drive enable register - - - - 0 0 0 0 a0 gpio5 output enable register - - - 0 0 0 0 0 a1 gpio5 output data register - - - 1 1 1 1 1 a2 gpio5 pin status register - - - - - - - - a3 gpio5 drive enable register - - - 0 0 0 0 0 90 gpio6 output enable register - - 0 0 0 0 0 0 91 gpio6 output data register - - 1 1 1 1 1 1 92 gpio6 pin status register - - - - - - - - 93 gpio6 drive enable register - - 0 0 0 0 0 0 wdt device configuration registers (ldn cr07) register 0x[hex] register name default value msb lsb f0 watchdog timer enable register - - - - - - - 1 f2 bus manual register 0 0 0 0 0 0 0 0 f3 key data register 0 0 0 0 0 0 0 0 f4 busin status register - - - - - - - - f5 wdt unit select register - 0 - 0 0 0 0 0 f6 wdt count register 0 0 0 0 1 0 1 0 f7 watchdog timer pme register 0 0 0 - - - - 0 pme, acpi, and eup power saving device configuration registers (ldn cr0a)
finte k feature integration technology inc. dec, 2010 v0.21p 44 f71869e register 0x[hex] register name default value msb lsb 30 pme device enable register - - - - - - - 0 e0 eup enable register 0 - - - - - 0 0 e1 eup control register 1 1 0 0 1 1 0 0 e2 eup control register - 0 1 1 1 1 0 - e3 eup psin deb-register 0 0 0 1 0 0 1 1 e4 eup rsmrst deb-register 0 0 0 0 1 0 0 1 e5 eup psout deb-register 1 1 0 0 0 1 1 1 e6 eup pson deb-register 0 0 0 0 1 0 0 1 e7 eup s5 deb-register 0 1 1 0 0 0 1 1 e8 wakeup enable register 0 - 0 0 1 0 0 0 ed eup wdt control register - - - - - - 0 0 ee eup wdt timer - - - - - - - 0 f0 pme event enable register 1 0 0 0 0 0 0 0 0 f1 pme event enable register 2 - - - - - 0 0 0 f2 pme event status register 1 - - - - - 0 0 0 f3 pme event status register 2 - - - - - - - - f4 keep last state select register 0 0 0 0 0 1 1 0 f5 vddok delay select register 0 0 0 1 1 1 0 0 f6 pcirst control register 0 0 - 1 1 1 1 1 f7 power sequence control register 1 0 0 0 0 1 1 0 f8 led vcc control register 0 - 0 0 0 0 0 0 f9 led vsb control register - - 0 0 0 0 0 0 fe ri de-bounce select register - - 0 0 0 0 0 0 6.1 global control registers 6.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the regi ster and device powered by vdd ( vcc ). 6.1.2 logic device number register (ldn) ? index 07h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 45 f71869e 7-0 ldn r/w 00h 00h: select fdc device co nfiguration registers. 01h: select uart 1 device configuration registers. 02h: select uart 2 device configuration registers. 03h: select parallel port devic e configuration registers. 04h: select hardware monitor dev ice configuration registers. 05h: select kbc device co nfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select wdt device c onfiguration registers. 0ah: select pme & acpi device configuration registers. 6.1.3 chip id register 1 ? index 20h bit name r/w default description 7-0 chip_id1 r 8h chip id1 6.1.4 chip id register 2 ? index 21h bit name r/w default description 7-0 chip_id2 r 14h chip id2 6.1.5 vendor id register 1 ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id1 6.1.6 vendor id register 2 ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id2 6.1.7 uart irq sharing register ? index 26h bit name r/w default description 7 clk24m_sel r/w 0 0: clkin is 48mhz 1: clkin is 24mhz 6-3 reserved - - reserved.
finte k feature integration technology inc. dec, 2010 v0.21p 46 f71869e 2 tx_del_1bit r/w 0 0: uart transmits data immediately after writing thr. 1: uart transmits data delay one bit time after writing thr. 1 irq_mode r/w 0 0: pci irq sharing mode (low level). 1: isa irq sharing mode (low pulse). 0 irq_shar r/w 0 0: disable irq sharing of two uart devices. 1: enable irq sharing of two uart devices. 6.1.8 configuration port select register ? index 27h bit name r/w default description 7-5 reserved - - reserved. 4 port_4e_en r/w - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by sout1/ config4e_2e. pull down to select port 2e/2f. 3-1 reserved - - reserved. 0 timing_en r - this bit is the pin status of timing_gpio pin. 0: disable power sequence control. 1: enable power sequence control. 6.1.9 multi-function select register 1 ? index 28h (powered by vsb3v) bit name r/w default description 7-6 reserved r/w 0 reserved 5 pwr_st1_en r/w 1 0: st1/gpio05 functions as gpio05. 1: st1/gpio05 functions as st1. 4 pwr_st2_en r/w 1 0:st2/slotocc#/gpio04 functions as slotocc#/gpio04 determined by gpio04_en. 1: st2/slotocc#/gpio04 functions as st2. 3 reserved r/w 1
finte k feature integration technology inc. dec, 2010 v0.21p 47 f71869e 2 gpio04_en r/w 0 0:st2/slotocc#/gpio04 functions as slotocc# if pwr_st2_en is not set. 1: st2/slotocc#/gpio04 functions as gpio04 if pwr_st2_en is not set. 1-0 reserved r/w 0 reserved 6.1.10 multi-function select register 2 ? index 29h (powered by vsb3v) bit name r/w default description 7 gpio17_en r/w 0 cpu_pwrgd/gpio17 function select. 0: the pin function is cpu_pwrgd. 1: the pin function is gpio17. 6 gpio16_en r/w 1 gpio16/led_vcc function select. 0: the pin function is led_vcc. 1: the pin function is gpio16. 5 gpio15_en r/w 1 gpio15/led_vsb/alert# function select. if led_vsb_en is set, the ping function is led_vsb, otherwise the pin function is determined by this bit: 0: the pin function is alert#. 1: the pin function is gpio15. 4 gpio14_en r/w 0 wdtrst#/gpio14 function select. 0: the pin function is wdtrst#. 1: the pin function is gpio14. 3 gpio13_en r/w 1 atx_pwrgdsw/gpio13/beep function select. if atx_pwrgdsw_en is set , the ping function is atx_pwrgdsw, otherwise the pin function is determined by this bit: 0: the pin function is beep. 1: the pin function is gpio13. 2 gpio12_en r/w 1 gpio12/ rstcon#/fanctl1 function select. 0: the pin function is fanctl1. 1: the pin function is gpio12.
finte k feature integration technology inc. dec, 2010 v0.21p 48 f71869e 1 gpio11_en r/w 1 pcirst5#/gpio11/ibx_sda function select. if ibx_alt_en is set , the ping f unction is ibx_sda, otherwise the pin function is determined by this bit: 0: the pin function is pcirst5#. 1: the pin function is gpio11. 0 gpio10_en r/w 1 pcirst4#/gpio10/ibx_sc l function select. if ibx_alt_en is set , the ping function is ibx_scl, otherwise the pin function is determined by this bit: 0: the pin function is pcirst4#. 1: the pin function is gpio10. 6.1.11 multi-function select register 3 ? index 2ah (powered by vsb3v) bit name r/w default description 7 reserved r/w 0 reserved 6 ibx_alt_en r/w 0 alternative ibx pin enable. 0: disable ibx alternative pins. 1: enable ibs alternative pins. see gpio11_en and gpio10_en for detail. 5 led_vsb_en r/w 0 0: disable led_vsb from gpio15/led_vsb/alert# 1: enable led_vsb from gpio15/led_vsb_alert#. 4 rstcon_pin_en r/w 0 rstcon# enable register: 0: the pin function of gpio12/ rstcon#/fanctl1 is gpio12/ fanctl1 1: the pin function of gpio12/rstcon#/fanctl1 is rstcon#. 3 atx_ pwrgdsw _en r/w 1 atx_pwrgdsw enable register: 0: the pin function of atx_pwrgdsw /gpio13/beep is determined by gpio13_en. 1: the pin function is atx_pwrgdsw. 2 fdc_gp_en r/w 1 set ?1? will disable fdc and change the fdc pins to gpios. 1 ur2_gp_en2 r/w 1 set ?1? will change uart2 modem control pins to gpios.
finte k feature integration technology inc. dec, 2010 v0.21p 49 f71869e 0 ur2_gp_en1 r/w 1 set ?1? will change uart2 sin/sout pins to gpios. set ur2_gp_en1 and ur2_gp_en2 will also disable uart2. 6.1.12 multi-function select register 4 ? index 2bh (powered by vsb3v) bit name r/w default description 7 gpio47_en r/w 0 pson#/gpio47 function select. 0: the pin function is pson#. 1: the pin function is gpio47. 6 gpio46_en r/w 0 pwsout#/gpio46 function select. 0: the pin function is pwsout#. 1: the pin function is gpio46. 5 gpio45_en r/w 0 pwsin#/gpio45 function select. 0: the pin function is pwsin#. 1: the pin function is gpio45. 4 gpio44_en r/w 0 atxpg_in/gpio44 function select. 0: the pin function is atxpg_in. 1: the pin function is gpio44. 3 gpio43_en r/w 1 gpio43/irrx function select. 0: the pin function is irrx. 1: the pin function is gpio43. 2 gpio42_en r/w 1 gpio42/irtx function select. 0: the pin function is irtx. 1: the pin function is gpio42. 1 gpio41_en r/w 1 fanctrl3/gpio41 function select. 0: the pin function is fanctrl3. 1: the pin function is gpio41.
finte k feature integration technology inc. dec, 2010 v0.21p 50 f71869e 0 gpio40_en r/w 1 fanin3/gpio40 function select. 0: the pin function is fanin3. 1: the pin function is gpio40. 6.1.13 wakeup control register ? index 2dh (powered by vbat) bit name r/w default description 7 slot_pwr_sel r/w 0 0: slotocc# is pull-up to vsb3v. 1: slotocc# is pull-up to vbat. 6 vsbok_hys_dis r/w 0 set ?1? to disable vsbok hysteresis. 5 vsbok_level _sel r/w 1 0: vsb3v power good level is 3. 05v and not good level is 2.95v. 1: vsb3v power good level is 2.8v and not good level is 2.5v. by vsbok_hys_dis and vsbok _lvl_sel, rsmrst# falling edge could be determined: 00: when vsb3v is lower than 2.95v. 01: when vsb3v is lower than 2.5v. 10: when vsb3v is lower than 3.05v. 11: when vsb3v is lower than 2.8v. 4 key_sel_add r/w 0 this bit is added to add more wakeup key function. 3 wakeup_en r/w 1 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up.
finte k feature integration technology inc. dec, 2010 v0.21p 51 f71869e 2-1 key_sel r/w 00 this registers select the keyboar d wake up key. accompanying with key_sel_add, there are eight wakeup keys: key_sel_add key_sel wakeup key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + space 0 11 any key 1 00 windows wakeup 1 01 windows power 1 10 ctrl + alt + space 1 11 space 0 mo_sel r/w 0 this register selects the mouse wake up key. 0: wake up by click. 1: wake up by click and movement. 6.2 fdc registers (cr00) 6.2.1 fdc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 fdc_en r/w 1 0: disable fdc. 1: enable fdc.
finte k feature integration technology inc. dec, 2010 v0.21p 52 f71869e 6.2.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of fdc base address. 6.2.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f0h the lsb of fdc base address. 6.2.4 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selfdcirq r/w 06h select the irq channel for fdc. 6.2.5 dma channel select register ? index 74h bit name r/w default description 7-3 reserved - - reserved. 2-0 selfdcdma r/w 010 select the dma channel for fdc. 6.2.6 fdd mode register ? index f0h bit name r/w default description 7 fdc_sw_pd r/w 0 write ?1? to software power down fdc. 6-5 reserved - - reserved. 4 fdc_sw_wp r/w 0 write ?1? to this bit will force fd c to write protect. otherwise, write protect is controlled by hardware pin wp#. 3-2 if_mode r/w 11 00: model 30 mode. 01: ps/2 mode. 10: reserved. 11: at mode (default). 1 fdmamode r/w 1 0: enable burst mode. 1: non-busrt mode (default). 0 en3mode r/w 0 0: normal floppy mode (default). 1: enhanced 3-mode fdd.
finte k feature integration technology inc. dec, 2010 v0.21p 53 f71869e 6.2.7 fdd drive type register ? index f2h bit name r/w default description 7-2 reserved - - reserved. 1-0 fdd_type r/w 11 fdd drive type. 6.2.8 fdd selection register ? index f4h bit name r/w default description 7-5 reserved - - reserved. 4-3 fdd_drt r/w 00 data rate table select, refer to table a. 00: select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 mega tape. 11: reserved. 2 reserved - - reserved. 1-0 fdd_dt r/w 00 drive type select, refer to table b. table a data rate table select data rate selected data rate densel fdd_drt[1] fdd_drt[0] datarate1 datarate0 mfm fm 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 0 0 1 1 1meg --- 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 0 1 1 1 1meg --- 1 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0 1 0 1 1 1meg --- 1
finte k feature integration technology inc. dec, 2010 v0.21p 54 f71869e table b 6.3 uart1 registers (cr01) 6.3.1 uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur1_en r/w 1 0: disable uart 1. 1: enable uart 1. 6.3.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart 1 base address. 6.3.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 1 base address. 6.3.4 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur1irq r/w 4h select t he irq channel for uart 1. 6.3.5 rs485 enable register ? index f0h bit name r/w default description drive type fdd_dt1 fdd_dt0 drvden0 remark 0 0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? 1/1.6/1 mb 3.5? ( 0 1 datarate1 1 0 densel# 1 1 datarate0
finte k feature integration technology inc. dec, 2010 v0.21p 55 f71869e 7-6 reserved - - reserved. 5 rs485_inv - - write ?1? will invert the rts# if rs485_en is set. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. rts# drive high when transmitting data, otherwise is kept low. 3-0 reserved - - reserved. 6.4 uart2 registers (cr02) 6.4.1 uart 2 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur2_en r/w 1 0: disable uart 2. 1: enable uart 2. 6.4.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of uart 2 base address. 6.4.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the lsb of uart 2 base address. 6.4.4 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selur2irq r/w 3h select t he irq channel for uart 2. 6.4.5 rs485 enable register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 rs485_inv - - write ?1? will invert the rts# if rs485_en is set.
finte k feature integration technology inc. dec, 2010 v0.21p 56 f71869e 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. rts# drive high when transmitting data, otherwise is kept low. 3 rxw4c_ir r/w 0 0: no reception delay when sir is changed form tx to rx. 1: reception delays 4 characters time when sir is changed form tx to rx. 2 txw4c_ir r/w 0 0: no transmission delay when sir is changed form rx to tx. 1: transmission delays 4 characters time when sir is changed form rx to tx. 1-0 reserved - - reserved. 6.4.6 sir mode control register ? index f1h bit name r/w default description 7 reserved - - reserved. 6 reserved - - reserved. 5 reserved - - reserved. 4-3 irmode r/w 00 00: disable ir function. 01: disable ir function. 10: irda function, active pulse is 1.6us. 11: irda function, active pulse is 3/16 bit time. 2 hduplx r/w 1 0: sir is in full duplex mode for loopback test. txw4c_ir and rxw4c_ir are of no use. 1: sir is in half duplex mode. 1 txinv_ir r/w 0 0: irtx is in normal condition. 1: inverse the irtx. 0 rxinv_ir r/w 0 0: irrx is in normal condition. 1: inverse the irrx.
finte k feature integration technology inc. dec, 2010 v0.21p 57 f71869e 6.5 parallel port register (cr03) 6.5.1 parallel port device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 prt_en r/w 1 0: disable parallel port. 1: enable parallel port. 6.5.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of parallel port base address. 6.5.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 78h the lsb of parallel port base address. 6.5.4 irq channel select register ? index 70h bit name r/w default description 7-5 reserved - - reserved. 3-0 selprtirq r/w 7h select the irq channel for parallel port. 6.5.5 dma channel select register ? index 74h bit name r/w default description 7-5 reserved - - reserved.
finte k feature integration technology inc. dec, 2010 v0.21p 58 f71869e 4 ecp_dma_mode r/w 0 0: non-burst mode dma. 1: enable burst mode dma. 3 reserved - - reserved. 2-0 selprtdma r/w 011 select the dma channel for parallel port. 6.5.6 prt mode select register ? index f0h bit name r/w default description 7 spp_irq_mode r/w 0 interrupt mode in non-ecp mode. 0: level mode. 1: pulse mode. 6-3 ecp_fifo_thr r/w 1000 ecp fifo threshold. 2-0 prt_mode r/w 010 000: standard and bi-direction (spp) mode. 001: epp 1.9 and spp mode. 010: ecp mode (default). 011: ecp and epp 1.9 mode. 100: printer mode. 101: epp 1.7 and spp mode. 110: reserved. 111: ecp and epp1.7 mode.
finte k feature integration technology inc. dec, 2010 v0.21p 59 f71869e 6.6 hardware monito r registers (cr04) 6.6.1 hardware monitor configuration registers ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. 6.6.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of ha rdware monitor base address. 6.6.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. 6.6.4 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the irq channel for hardware monitor. before the device registers, the followi ng is a register map order which show s a summary of all registers. please refer each one register if you want more detail information. register cr01 ~ cr03 ? configuration registers
finte k feature integration technology inc. dec, 2010 v0.21p 60 f71869e register cr0a ~ cr0f ? peci/tsi control register register cr10 ~ cr37 ? voltage setting register register cr40 ~ cr4f ? peci 3.0 command and register register cr60 ~ cr8e ? temperature setting register register cr90 ~ crdf ? fan control setting register ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf ? fan3 detail setting crc0 ~ crcf 6.6.5 configuration register ? index 01h bit name r/w default description 7-3 reserved - 0 reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. 6.6.6 configuration register ? index 02h bit name r/w default description 7 reserved r/w 0 dummy register. 6 case_beep_en r/w 0 0: disable case open event output via beep. 1: enable case open event output via beep. 5-4 ovt_mode r/w 0 00: the ovt# will be low active level mode. 01: the ovt# will be low pulse mode. 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 reserved r/w 0 dummy register. 2 case_smi_en r / w 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 alert_mode r/w 0 00: the alert# will be low active level mode. 01: the alert# will be high active level mode. 10: the alert# will indicate by 1hz led function. 11: the alert# will indicate by (400/800hz) beep output. 6.6.7 configuration register ? index 03h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 61 f71869e 7-1 reserved r/w 0 reserved 0 case_sts r/w 1 case open event status. write 1 to clear if case open event cleared. (this bit is powered by vbat.) 6.6.8 new tsi mode enable register ? index 07h bit name r/w default description 7-1 reserved - 0 reserved 0 new_tsi_mode r/w 0 set this bit to enable tsi new mode. please check cr0a for more detail. 6.6.9 configuration register ? index 08h bit name r/w default description 7-1 smbus_addr r/w 7?h26 when amd tsi or intel pch smbus is enabled, this byte is used as smbus_addr. smbus_addr[7:1] is the slave address sent by the embedded master to fetch the temperature. 0 reserved - - reserved 6.6.10 configuration register ? index 09h bit name r/w default description 7 - 1 i2c_addr r /w 0 i2c_addr[7:1] is the slave addres s sent by the embedded master when using a block write command 0 reserved r/w 0 reserved 6.6.11 configuration register ? index 0ah bit name r/w default description 7 beta_en r/w 0 0: disable the t1 beta compensation. 1: enable the t1 beta compensation. 6 intel_model r/w 1 0: amd model. 1: intel model. 5-4 reserved - 0 reserved. 3-2 vtt_sel r/w 0 peci (vtt) voltage select. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v
finte k feature integration technology inc. dec, 2010 v0.21p 62 f71869e 1 tsi_en r/w 0 0: disable the tsi function via peci/peci_req# or pci_rst4#/pci_rst5# pins. 1: enable the tsi function via peci/peci_req# or pci_rst4#/pci_rst5# pins. this bit accompanies with in tel_model, ibx_alt_en, peci_en, and it determines the availability of amd tsi, intel pch smbus, or peci. setting (cr07[0]-- new_tsi_mode = 0) intel_ model (cr0a, bit6) tsi_en (cr0a, bit1) peci_en (cr0a, bit0) ibx_alt_en (cr2a, bit6 in global configuration register) peci amd tsi intel pch smbus 0 0 x x n n n 0 1 x x n y n 1 0 1 x y n n 1 1 1 1 y n y 1 1 0 x n n y setting (cr07[0]-- new_tsi_mode = 1) intel_ model (cr0a, bit6) tsi_en (cr0a, bit1) peci_en (cr0a, bit0) ibx_alt_en (cr2a, bit6 in global configuration register) peci amd tsi intel pch smbus 0 0 x x n n n 0 1 x x n n y 1 0 1 x y n n 1 1 1 1 y y n 1 1 0 x n y n 0 peci_en r/w 0 0: disable peci function via peci/peci_req# pins 1: enable peci function via peci/peci_req# pins 6.6.12 configuration register ? index 0bh bit name r/w default description 7-4 cpu_sel r/w 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping() command to find cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 0, i.e. peci address is 0x31. 0100: cpu is in socket 0, i.e. peci address is 0x32. 1000: cpu is in socket 0, i.e. peci address is 0x33. others are reserved. 3-1 reserved - 0 reserved. 0 domain1_en r/w 0 if the cpu is selected as dual core. set this register 1 to read the temperature of domain1.
finte k feature integration technology inc. dec, 2010 v0.21p 63 f71869e 6.6.13 configuration register ? index 0ch bit name r/w default description 7-0 tcc_temp r/w 8?h55 tcc activation temperature. when peci is enabled, the absolute value of cpu temperature is calculated by the equation: cpu_temp = tcc_temp + peci reading. the range of this register is -128 ~ 127. 6.6.14 configuration register ? index 0dh bit name r/w default description 7-0 tsi_offset r/w 8?h00 tsi temperature offset for cpu when amd tsi or intel pch smbus is enabled, this byte is used as the offset to be added to the temperature reading of cpu. 6.6.15 configuration register ? index 0fh bit name r/w default description 7-6 reserved - 0 reserved. 5 peci_req_en r / w 1 0: disable the peci_req# function. 1: enable the peci_req# function. 4-2 reserved - 0 reserved. 1-0 dig_rate_sel r/w 0 digital temperatures monitoring rate for peci, amd tsi, or intel pch smbus. the rate is calculated by 20hz/(dig_rate_sel + 1). 6.6.16 over-voltage shut down enable register ? index 10h bit name r/w default description 7 reserved - 0 reserved. 6 v6_ovp_en r/w 0 over-voltage shut down enable for vin6 5 v5_ovp_en r/w 0 over-voltage shut down enable for vin5 4-1 reserved - 0 reserved 0 v0_ovp_en r/w 0 over-voltage shut down enable for vcc3v 6.6.17 over-voltage status register (powered by vbat) ? index 11h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 64 f71869e 7-6 reserved - 0 reserved. 0 v_exc_ovv r/w c 0 this bit is over-voltage status. once one of the monitored voltages (vcc3v, vin5, vin6) over its related over-voltage limits and its related over-voltage shut down enable bit is set, this bit will be set to 1. write a 1 to this bit will clear it to 0. (this bit is powered by vbat) 6.6.18 voltage reading and limit ? index 20h- 37h address attribute default value description 20h r -- vcc3v reading. the unit of reading is 8mv. 21h r -- vin1 (vcore) reading. the unit of reading is 8mv. 22h r -- vin2 reading. the unit of reading is 8mv. 23h r -- vin3 reading. the unit of reading is 8mv. 24h r -- vin4 reading. the unit of reading is 8mv. 25h r -- vin5 reading. the unit of reading is 8mv. 26h r -- vin6 reading. the unit of reading is 8mv. 27h r -- vsb3v reading. the unit of reading is 8mv. 28h r -- vbat reading. the unit of reading is 8mv. 29~30h r ff reserved 2dh ro -- fan1 present fan duty reading 2eh ro -- fan2 present fan duty reading 2fh ro -- fan3 present fan duty reading 36h r/w ff vin5 over-voltage limit (v5_ovv _limit). the unit is 9mv. (this byte is powered by vbat.) 37h r/w ff vin6 over-voltage limit (v6_ovv _limit). the unit is 9mv. (this byte is powered by vbat.) 3fh w ff write bit 0 to ?1? to select ovp start monitor after pwrok ready. peci 3.0 command and register 6.6.19 peci configuration register ? index 40h bit name r/w default description 7 rdiamsr_cmd_en r/w 0 when peci temperature monitoring is enabled, set this bit 1 will generate a rdiamsr() command before a gettemp() command. 6 c3_update_en r/w 0 if rdiamsr_cmd_en is not set to 1, the temperature data is not allowed to be updated when the comp letion code of rdiamsr() is 0x82.
finte k feature integration technology inc. dec, 2010 v0.21p 65 f71869e 5-4 reserved r - reserved 3 c3_ptemp_en r/w 0 set this bit 1 to enable updateing positive value of temperature if the completion code of rdiamsr() is 0x82. 2 c0_ptemp_en r/w 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 1 c3_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is 0x82. 0 c0_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 6.6.20 peci master control register ? index 41h bit name r/w default description 7 peci_cmd_star t w - write 1 to this bit to start a peci command when using as a peci master. (peci_pending must be set to 1) 6-5 reserved r - reserved 4 peci_pending r/w 0 set this bit 1 to stop monitoring peci temperature. 3 reserved r - reserved 2-0 peci_cmd r/w 3?h0 peci command to be used by peci master. 000: ping() 001: getdib() 010: gettemp() 011: rdiamsr() 100: rdpkgconfig() 101: wrpkgconfig() others: reserved 6.6.21 peci master status register ? index 42h bit name r/w default description 7-2 reserved r - reserved 1 peci_fcs_err r/w c - this bit is the fcs error status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 0 peci_finish r/w c - this bit is the command finish status of peci master commands. write this bit 1 or read this by te will clear this bit to 0. 6.6.22 peci master data0 register ? index 43h bit name r/w default description 7-0 peci_data0 r/w 0 for rdiamsr(), rdpkgconfig() and wrpkgconfig() command, this byte represents ?host id[7:1] & retry[0]?. please refer to peci interface specification for more detail. 6.6.23 peci master data1 register ? index 44h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 66 f71869e 7-0 peci_data1 r/w 0 for rdiamsr() , this byte represents ?processor id?. for rdpkgconfig() and wrpkgconfig() , this byte represents ?index?. please refer to peci interface specification for more detail. 6.6.24 peci master data2 register ? index 45h bit name r/w default description 7-0 peci_data2 r/w 0 for rdiamsr(), this byte is the least significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the least significant byte of ?parameter?. please refer to peci interface specification for more detail. 6.6.25 peci master data3 register ? index 46h bit name r/w default description 7-0 peci_data3 r/w 0 for rdiamsr(), this byte is the most significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the most significant byte of ?parameter?. please refer to peci interface specification for more detail. 6.6.26 peci master data4 register ? index 47h bit name r/w default description 7-0 peci_data4 r/w 0 for getdib() , this byte represents ?device info? for gettemp(), this byte represents the least significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte is ?completion code?. for wrpkgconfig(), this byte represents ?data[7:0]? 6.6.27 peci master data5 register ? index 48h bit name r/w default description 7-0 peci_data5 r/w 0 for getdib() , this byte represents ?revision number? for gettemp(), this byte represents the most significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte represents ?data[7:0]? for wrpkgconfig(), this byte represents ?data[15:8]? 6.6.28 peci master data6 register ? index 49h bit name r/w default description 7-0 peci_data6 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[15:8]?. for wrpkgconfig(), this byte represents ?data[23:16]? 6.6.29 peci master data7 register ? index 4ah bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 67 f71869e 7-0 peci_data7 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[23:16]?. for wrpkgconfig(), this byte represents ?data[31:24]? 6.6.30 peci master data8 register ? index 4bh bit name r/w default description 7-0 peci_data8 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[31:24]?. for wrpkgconfig(), this byte represents ?aw fcs? 6.6.31 peci master data9 register ? index 4ch bit name r/w default description 7-0 peci_data9 r/w 0 for rdiamsr(), this byte represents ?data[39:32]?. for wrpkgconfig(), this byte represents ?completion code? 6.6.32 peci master data10 register ? index 4dh bit name r/w default description 7-0 peci_data10 r/w 0 for rdiamsr(), th is byte represents ?data[47:40]?. 6.6.33 peci master data11 register ? index 4eh bit name r/w default description 7-0 peci_data11 r/w 0 for rdiamsr(), th is byte represents ?data[55:48]?. 6.6.34 peci master data12 register ? index 4fh bit name r/w default description 7-0 peci_data12 r/w 0 for rdiamsr(), th is byte represents ?data[63:56]?. temperature setting 6.6.35 temperature pme# enable register ? index 60h bit name r/w default description 7 en_ t3_ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ovt_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds ovt setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp3 exceeds high limit setting.
finte k feature integration technology inc. dec, 2010 v0.21p 68 f71869e 2 en_ t2_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 0 if set this bit to 1, pme# signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved 6.6.36 temperature interrupt status register ? index 61h bit name r/w default description 7 t3_ovt_sts r/w 0 this bit gets 1 to indicate temp3 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, and write 0 to ignore. 6 t2_ovt _sts r/w 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 5 t1_ovt _sts r/w 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 4 reserved r/w 0 reserved 3 t3_exc _sts r/w 0 this bit gets 1 to indicate temp3 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis?. write 1 to clear this bit, write 0 to ignore. 2 t2_exc _sts r/w 0 this bit gets 1 to indicate temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 1 t1_exc _sts r/w 0 this bit gets 1 to indicate temp1 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 to ignore. 0 reserved r/w 0 reserved 6.6.37 temperature real time status register ? index 62h bit name r/w default description 7 t3_ovt r/w 0 set when the temp3 exceeds the ovt limit. clear when the temp3 is below the ?ovt limit ?hysteresis? temperature. 6 t2_ovt r/w 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature.
finte k feature integration technology inc. dec, 2010 v0.21p 69 f71869e 5 t1_ovt r/w 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 reserved r/w 0 reserved 3 t3_exc r/w 0 set when the temp3 exceeds the high limit. clear when the temp3 is below the ?high limit ?hysteresis? temperature. 2 t2_exc r/w 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 reserved r/w 0 reserved 6.6.38 temperature beep enable register ? index 63h bit name r/w default description 7 en_t3_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp3 exceeds ovt limit setting. 6 en_ t2_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 reserved r/w 0 reserved 3 en_ t3_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp3 exceeds high limit setting. 2 en_ t2_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds high limit setting. 0 reserved r/w 0 reserved 6.6.39 t1 ovt and high limit temperature select register ? index 64h bit name r/w default description 7-6 reserved r/w 0 reserved
finte k feature integration technology inc. dec, 2010 v0.21p 70 f71869e 5-4 ovt_temp_sel r/w 0 select the source temperature for t1 ovt limit. 0: select t1 to be compared to temperature 1 ovt limit. 1: select cpu temperature fr om peci to be compared to temperature 1 ovt limit. 2: select cpu temperature from amd tsi or intel pch smbus to be compared to temperature 1 ovt limit. 3: select the max temperature from intel pch smbus to be compared to temperature 1 ovt limit. 3-2 reserved r/w 0 reserved 1-0 high_ temp_sel r/w 0 select the source temperature for t1 high limit. 0: select t1 to be compared to temperature 1 high limit. 1: select cpu temperature fr om peci to be compared to temperature 1 high limit. 2: select cpu temperature from amd tsi or intel pch smbus to be compared to temperature 1 high limit. 3: select the max temperature from intel pch smbus to be compared to temperature 1 high limit. 6.6.40 ovt and alert output enable register 1 ? index 66h bit name r/w default description 7 en_t3_alert r 0 enable temperature 3 alert event (a sserted when temperature over high limit) 6 en_t2_alert r 0 enable temperature 2 alert event (a sserted when temperature over high limit) 5 en_t1_alert r 0 enable temperature 1 alert event (a sserted when temperature over high limit) 4 reserved r 0 reserved. 3 en_t3_ovt r/w 0 enable over temperat ure (ovt) mechanism of temperature3. 2 en_t2_ovt r/w 0 enable over temperat ure (ovt) mechanism of temperature2. 1 en_t1_ovt r/w 1 enable over temperat ure (ovt) mechanism of temperature1. 0 reserved r 0h reserved. 6.6.41 reserved ? index 67~69h bit name r/w default description 7-0 reserved - - reserved
finte k feature integration technology inc. dec, 2010 v0.21p 71 f71869e 6.6.42 temperature sensor type register ? index 6bh bit name r/w default description 7-4 reserved ro 0 reserved 3 t3_mode r/w 1 0: temp3 is connected to a thermistor 1: temp3 is connected to a bjt.(default) 2 t2_mode r/w 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved r 0 reserved 6.6.43 temp1 limit hyst ersis select register ? index 6ch bit name r/w default description 7-4 temp1_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the (boundary ? hysteresis ). 3-0 reserved r 0h reserved 6.6.44 temp2 and temp3 limit hystersis select register ? index 6dh bit name r/w default description 7-4 temp3_hys r/w 2h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 3-0 temp2_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 6.6.45 diode open status register ? index 6fh bit name r/w default description 7-6 reserved r - reserved 5 peci_open r - when peci interface is enabled, ?1? indicates an error code (0x0080 or 0x0081) is received from peci slave. 4 tsi_open r - when tsi interface is enabled, ?1? indicates the error of not receiving nack bit or a timeout occurred. 3 t3_diode_open r - ?1? indicates external diode 3 is open 2 t2_diode_open r - ?1? indicates external diode 2 is open or short 1 t1_diode_open r - ?1? indicates external diode 1 is open or short 0 reserved r - reserved
finte k feature integration technology inc. dec, 2010 v0.21p 72 f71869e 6.6.46 temperature ? index 70h- 8dh address attribute default value description 70h reserved ffh reserved 71h reserved ffh reserved 72h r -- temperature 1 reading. the unit of reading is 1oc.at the moment of reading this register. 73h r -- reserved 74h r -- temperature 2 reading. the unit of reading is 1oc.at the moment of reading this register. 75h r -- reserved 76h r -- temperature 3 reading. the unit of reading is 1oc.at the moment of reading this register. 77-79h r -- reserved 7ah r -- the data of cpu temperature from digital interface after iir filter. (available if intel ibx or amd tsi interface is enabled) 7bh r -- the raw data of pch temperature from digital interface. (only available if intel ibx interface is enabled) 7ch r -- the raw data of mch read from digita l interface. (only available if intel ibx interface is enabled) 7dh r -- the raw data of maximum temperature between cpu/pch/mch from digital interface. (only ava ilable if intel ibx interface is enabled) 7eh r -- the data of cpu temperature from digital interface after iir filter. (only available if peci interface is enabled) 7fh reserved ffh reserved 80h reserved ffh reserved 81h reserved ffh reserved 82h r/w 64h temperature sensor 1 ovt limit. the unit is 1oc. 83h r/w 55h temperature sensor 1 high limit. the unit is 1oc. 84h r/w 64h temperature sensor 2 ovt limit. the unit is 1oc. 85h r/w 55h temperature sensor 2 high limit. the unit is 1oc. 86h r/w 55h temperature sensor 3 ovt limit. the unit is 1oc. 87h r/w 46h temperature sensor 3 high limit. the unit is 1oc.
finte k feature integration technology inc. dec, 2010 v0.21p 73 f71869e 88-8bh r -- reserved 8c~8dh r ffh reserved 6.6.47 temperature filter select register ? index 8eh bit name r/w default description 7-6 iir-queur3 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 5-4 iir-queur2 r/w 1h the queue time for second filter to quickly update values. 00: 8 times. 01: 12 times. 10: 16 times. (default) 11: 24 times. 3-2 iir-queur1 r/w 1h the queue time for second filter to quickly update values. 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. 1-0 iir-queur_dig r/w 1h the queue time for second filter to quickly update values. (for cpu temperature from peci or tsi interface) 00: 8 timers. 01: 12 times. 10: 16 times. (default) 11: 24 times. fan control setting 6.6.48 fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved r 0 reserved 2 en_fan3_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt set this bit 1 to enable pme# function for fan3.
finte k feature integration technology inc. dec, 2010 v0.21p 74 f71869e 1 en_fan2_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2. 0 en_fan1_pme r/w 0 a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. 6.6.49 fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved r 0 reserved 2 fan3_sts r/w -- this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w -- this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w -- this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 6.6.50 fan real time status register ? index 92h bit name r/w default description 7-3 reserved -- 0 reserved 2 fan3_exc r -- this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. 1 fan2_exc r -- this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. 0 fan1_exc r -- this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or when duty not zero but fan stop over then 3 sec. 6.6.51 fan beep# enable register ? index 93h bit name r/w default description 7 full_with_ t3_en r/w 0 set one will enable fan to force full speed when t3 over high limit.
finte k feature integration technology inc. dec, 2010 v0.21p 75 f71869e 6 full_with_ t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_ t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4 reserved - - reserved 3 reserved - - reserved. 2 en_fan3_ beep r/w 0 a one enables the corr esponding interrupt status bit for beep. 1 en_fan2_ beep r/w 0 a one enables the corr esponding interrupt status bit for beep. 0 en_fan1_ beep r/w 0 a one enables the corr esponding interrupt status bit for beep. 6.6.52 fan type select register ? index 94h fan_prog_sel = 0 bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl3 0: fanctrl3 is pull up by external resistor. 1: fanctrl3 is pull down by internal 100k resistor. 3-2 fan2_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl2 0: fanctrl2 is pull up by external resistor. 1: fanctrl2 is pull down by internal 100k resistor.
finte k feature integration technology inc. dec, 2010 v0.21p 76 f71869e 1-0 fan1_type r/w 2?b 0s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctrl1 0: fanctrl1 is pull up by external resistor. 1: fanctrl1is pull down by internal 100k resistor. s : register default values are decided by trapping. fan_prog_sel = 1 bit name r/w default description 7-0 fan1_base _temp r/w 0 this register is used to set the base temperature for fan1 temperature adjustment. the fan1 temperature is calculated according to the equation: tfan1 = tnow + (ta ? tb)*ct where tnow is selected by fan1_temp_sel_dig and fan1_temp_sel. tb is this register, ta is selected by tfan1_adj_sel and ct is selected by tfan1_adj_up_rate/tfan1_adj_dn_rate. to access this register, fan_prog_ sel(cr9f[7]) must set to ?1?. 6.6.53 fan1 temperature adjust rate register ? index 95h (fan_prog_sel = 1) bit name r/w default description 7 reserved - - reserved 6-4 tfan1_adj_up _rate 3?h0 this selects the weighting of the difference between ta and tb if ta is higher than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 3 reserved - - reserved
finte k feature integration technology inc. dec, 2010 v0.21p 77 f71869e 2-0 tfan1_adj_dn _rate r/w 3?h0 this selects the weighting of the difference between ta and tb if ta is lower than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 6.6.54 fan mode select register ? index 96h fan_prog_sel = 0 bit name r/w default description 7-6 reserved - - reserved 5-4 fan3_mode r/w 01 00: auto fan speed control. fan spee d will follow different temperature by different rpm defined in 0xc6-0xce. 01: auto fan speed control. fan spee d will follow different temperature by different duty cycle defined in 0xc6-0xce. 10: manual mode fan control. user can write expected rpm count to 0xc2-0xc3, and f71869e will adjus t duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed automatically. 11: manual mode fan control. user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xc3, and f71869e will output this desired duty or voltage to control fan speed. 3-2 fan2_mode r/w 01 00: auto fan speed control. fan spee d will follow different temperature by different rpm defined in 0xb6-0xbe. 01: auto fan speed control. fan spee d will follow different temperature by different duty cycle (voltage) defined in 0xb6-0xbe. 10: manual mode fan control. user can write expected rpm count to 0xb2-0xb3, and f71869e will adjust duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and f71869e will output this desired duty or voltage to control fan speed.
finte k feature integration technology inc. dec, 2010 v0.21p 78 f71869e 1-0 fan1_mode r/w 01 00: auto fan speed control. fan spee d will follow different temperature by different rpm defined in 0xa6-0xae. 01: auto fan speed control. fan spee d will follow different temperature by different duty cycle defined in 0xa6-0xae. 10: manual mode fan control, user can write expected rpm count to 0xa2-0xa3, and f71869e will auto cont rol duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed automatically. 11: manual mode fan control, user can write expected duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, and f71869e will output this desired duty or voltage to control fan speed. fan_prog_sel = 1 bit name r/w default description 7-3 reserved - - reserved 2-0 tfan1_adj_sel r/w 0h this selects which temperature to be used as ta for fan1 temperature adjustment. 000: peci (cr7eh) 001: t1 (cr72h) 010: t2 (cr74h) 011: t3 (cr76h) 100: digital t1 (cr7ah) 101: digital t1 (cr7bh) 110: digital t2 (cr7ch) 111: digital t3 (cr7dh) otherwise: ta will be 0. to access this register fa n_prog_sel must set to ?1?. 6.6.55 auto fan1 and fan2 boundary hystersis select register ? index 98h bit name r/w default description 7-4 fan2_hys r/w 4h boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 3-0 fan1_hys r/w 4h boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ).
finte k feature integration technology inc. dec, 2010 v0.21p 79 f71869e 6.6.56 auto fan3 boundary hystersis select register ? index 99h bit name r/w default description 7-4 reserved - - reserved. 3-0 fan3_hys r/w 2h boundary hysteresis. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 6.6.57 auto fan up speed update rate select register ? index 9bh fan_prog_sel = 0 bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_up_rate r/w 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 3-2 fan2_up_rate r/w 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_up_rate r/w 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz fan_prog_sel = 1 bit name r/w default description 7-6 reserved - - reserved. 5-4 fan3_dn_rate r/w 01 fan3 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz
finte k feature integration technology inc. dec, 2010 v0.21p 80 f71869e 3-2 fan2_dn_rate r/w 01 fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_dn_rate r/w 01 fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 6.6.58 fan1 and fan2 start up duty-cycle/voltage ? index 9ch bit name r/w default description 7-4 fan2_stop _duty r/w 5h when fan start, the fan_ctrl2 will in crease duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fan_ctrl 2 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop _duty r/w 5h when fan start, the fan_ctrl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 1 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 6.6.59 fan3 start up duty-cycle/voltage ? index 9dh bit name r/w default description 7-4 reserved - - reserved. 3-0 fan3_stop_ duty r/w 5h when fan start, the fan_ctrl 3 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fan_ctrl 3 will decrease duty-cycle to 0 when the pwm duty cycle is less than this (value x 4). 6.6.60 fan programmable duty-cycle/voltage loaded after power-on ? index 9eh bit name r/w default description 7-0 prog_duty_val r/w 66h this byte will be immediately loaded as fan duty value after vdd is powered on if it has been programmed before shut down.
finte k feature integration technology inc. dec, 2010 v0.21p 81 f71869e 6.6.61 fan fault time register ? index 9fh bit name r/w default description 7 fan_prog_sel r/w 0 0: select fan type (94h) and fan mode (96h) for fan 1 to fan 3. 1: select fan1 multi-temp settings (94h, 95h, 96h and afh). 6-5 reserved - - reserved 4 full_duty_sel r/w - 0: the fan duty is 100% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull down by external resistor) 1: the fan duty is 40% and will be loaded immediately after vdd is powered on if cr9e is not been programmed before shut down. (pull up by internal 47k resistor). this register is power on trap by dtr1#. 3-0 f_fault_time r/w ah this register determines the time of fan fault. the condition to cause fan fault event is: when pwm_duty reaches ffh, if the fan speed count can?t reach the fan expect count in time. the unit of this register is 1 second. the default value is 11 seconds. (set to 0 , means 1 seconds. ; set to 1, means 2 seconds. set to 2, means 3 seconds. ?. ) another condition to cause fan f ault event is fan stop and the pwm duty is greater than the minimum duty programmed by the register index 9c-9dh. 6.6.62 fan1 index a0h~afh address attribute default value description a0h ro 8?h0f fan1 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h r/w 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count val ue (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w 8?h01 rpm mode(cr96 bit0=0):
finte k feature integration technology inc. dec, 2010 v0.21p 82 f71869e fan1 expect speed count value (l sb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode (cr96 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). 6.6.63 vt1 boundary 1 temperature ? index a6h bit name r/w default description 7-0 bound1tmp1 r/w 3ch (60 o c) the first boundary temperature for vt1 in temperature mode. when vt1 temperature exceeds this boundary, expected fan1 value will be loaded from segment 1 register (index aah). when vt1 temperature is under this boundary ? hysteresis, expected fan1 value will be loaded from segment 2 register (index abh). this byte is a 2?s complement value ranged from -128?c ~ 127?c. 6.6.64 vt1 boundary 2 temperature ? index a9h bit name r/w default description 7-0 bound2tmp1 r/w 1eh (30 o c) the second boundary temperature for vt1 in temperature mode. when vt1 temperature exceeds this boundary, fan1 expect value will load from segment 2 register (index abh). when vt1 temperature is under this boundary ? hysteresis, fan1 expect value will load from segment 3 register (index aeh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 6.6.65 fan1 segment 1 speed count ? index aah bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 83 f71869e 7 - 0 sec1speed1 r /w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.66 fan1 segment 2 speed count ? index abh bit name r/w default description 7 - 0 sec2speed1 r /w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.67 fan1 segment 3 speed count ? index aeh bit name r/w default description 7 - 0 sec3speed1 r /w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.68 fan1 temperature mapping select ? index afh bit name r/w default description 7 fan1_temp _sel_dig r/w 0 this bit companies with fan1_temp_sel select the temperature source for controlling fan1. 6 fan1_pwm _freq_sel r/w 0 set this bit to select fan2 pwm output frequency. 0: 23.5 khz 1: 220 hz 5 fan1_up_t_en r /w 0 set 1 to force fan1 to full speed if any temperature over its high limit. 4 fan1_ interpolation_en r/w 1 set 1 will enable the interpolat ion of the fan expect table.
finte k feature integration technology inc. dec, 2010 v0.21p 84 f71869e 3 fan1_jump _high_en r/w 1 this register controls the fan1 dut y movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec1speed1 register. this bit only activates in duty mode. 2 fan1_jump _low_en r/w 1 this register controls the fan1 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_rate_sel register. 1: the fan1 duty will directly jumps to the value of sec2speed1 register. this bit only activates in duty mode. 1 - 0 fan1_temp_sel r /w 01 this registers company with fan1_temp_sel_dig select the temperature source for controlling fan1. the following value is comprised by {fan1_temp_sel_dig, fan1_temp_sel} 000: fan1 follows peci temperature (cr7eh) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 3 (cr76h). 100: fan1 follows ibx/tsi cpu temperature (cr7ah) 101: fan1 follows ibx pch temperature (cr7bh). 110: fan1 follows ibx m ch temperature (cr7ch). 111: fan1 follows ibx maximum temperature (cr7dh). others are reserved. 6.6.69 fan2 index b0h~bfh address attribute default value description b0h ro 8?h0f fan2 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h r/w 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count val ue (msb), in auto fan mode(cr96
finte k feature integration technology inc. dec, 2010 v0.21p 85 f71869e bit3 ? 0) this register is auto updated by hardware. duty mode(cr96 bit2=1): this byte is reserved byte. b3h r/w 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb). 6.6.70 vt2 boundary 1 temperature ? index b6h bit name r/w default description 7-0 bound1tmp2 r/w 3ch (60 o c) the first boundary temperature for vt2 in temperature mode. when vt2 temperature exceeds this boundary, fan2 expect value will load from segment 1 register (index bah). when vt2 temperature is under this boundary ? hysteresis, fan2 expect value will load from segment 2 register (index bah). this byte is a 2?s complement value ranging from -128?c ~ 127?c. bit 7 will always be ?0? (always positi ve) if fan_neg_temp_en is ?0?. 6.6.71 vt2 boundary 2 temperature ? index b7h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 86 f71869e 7-0 bound2tmp2 r/w 1eh (30 o c) the second boundary temperature for vt2 in temperature mode. when vt2 temperature exceeds this boundary, fan2 expect value will load from segment 2 register (index bb)h. when vt2 temperature is under this boundary ? hysteresis, fan2 expect value will load from segment 3 register (index bbh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. bit 7 will always be ?0? (always positi ve) if fan_neg_temp_en is ?0?. 6.6.72 fan2 segment 1 speed count ? index bah bit name r/w default description 7 - 0 sec1speed2 r /w ffh (100%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.73 fan2 segment 2 speed count ? index bbh bit name r/w default description 7 - 0 sec2speed2 r /w d9h (85%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.74 fan2 segment 3 speed count ? index beh bit name r/w default description 7 - 0 sec3speed2 r /w 80h (50%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
finte k feature integration technology inc. dec, 2010 v0.21p 87 f71869e 6.6.75 fan2 temperature mapping select ? index bfh bit name r/w default description 7 fan2_temp_ sel_dig r/w 0 this bit companies with fan2_tem p_sel to select the temperature source for controlling fan2. 6 fan2_pwm_ freq_sel r/w 0 set this bit to select fan2 pwm output frequency. 0: 23.5 khz 1: 220 hz 5 fan2_up_t_en r /w 0 set 1 to force fan2 to full speed if any temperature over its high limit. 4 fan2_ interpolation_en r/w 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan2_jump_ high_en r/w 1 this register controls the fan2 duty movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec1speed2 register. this bit only activates in duty mode. 2 fan2_jump_ low_en r/w 1 this register controls the fan2 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_rate_sel register. 1: the fan2 duty will directly jumps to the value of sec2speed2 register. this bit only activates in duty mode. 1 - 0 fan2_temp_sel r /w 10 this registers companying with fan2_temp_sel_dig select the temperature source for controlling fan2. the following value is comprised by {fan2_temp_sel_dig, fan2_temp_sel} 000: fan2 follows peci temperature (cr7eh) 001: fan2 follows temperature 1 (cr72h). 010: fan2 follows temperature 2 (cr74h). 011: fan2 follows temperature 3 (cr76h). 100: fan2 follows ibex/tsi cpu temperature (cr7ah) 101: fan2 follows ibex pch temperature (cr7bh). 110: fan2 follows ibex m ch temperature (cr7ch). 111: fan2 follows ibex maxi mum temperature (cr7dh). otherwise: reserved.
finte k feature integration technology inc. dec, 2010 v0.21p 88 f71869e 6.6.76 fan3 index c0h- cfh address attribute default value description c0h ro 8?h0f fan3 count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h r/w 8?h00 rpm mode(cr96 bit4=0): fan3 expect speed count val ue (msb), in auto fan mode(cr96 bit5 ? 0) this register is auto updated by hardware. duty mode(cr96 bit4=1): this byte is reserved byte. c3h r/w 8?h01 rpm mode(cr96 bit4=0): fan3 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit4=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit5 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% c4h r/w 8?h03 fan3 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c5h r/w 8?hff fan3 full speed count reading (lsb). 6.6.77 vt3 boundary 1 temperature ? index c6h bit name r/w default description 7-0 bound1tmp3 r/w 3ch (60 o c) the first boundary temperature for vt3 in temperature mode. when vt3 temperature exceeds this boundary, fan3 expect value will load from segment 1 register (index ca)h. when vt3 temperature is under this boundary ? hysteresis, fan3 expect value will load from segment 2 register (index cah). this byte is a 2?s complement value ranging from -128?c ~ 127?c.
finte k feature integration technology inc. dec, 2010 v0.21p 89 f71869e 6.6.78 vt3 boundary 2 temperature ? index c9h bit name r/w default description 7-0 bound2tmp3 r/w 1eh (30 o c) the second boundary temperature for vt3 in temperature mode. when vt3 temperature exceeds this boundary, fan3 expect value will load from segment 2 register (index cb)h. when vt3 temperature is under this boundary ? hysteresis, fan3 expect value will load from segment 3 register (index cbh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 6.6.79 fan3 segment 1 speed count ? index cah bit name r/w default description 7 - 0 sec1speed3 r /w ffh (100%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100%:full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.80 fan3 segment 2 speed count ? index cbh bit name r/w default description 7 - 0 sec2speed3 r /w d9h (85%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 6.6.81 fan3 segment 3 speed count ? index ceh bit name r/w default description 7 - 0 sec3speed3 r /w 80h (50%) the meaning of this register is depending on the fan3_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section.
finte k feature integration technology inc. dec, 2010 v0.21p 90 f71869e 6.6.82 fan3 temperature mapping select ? index cfh bit name r/w default description 7 fan3_temp_ sel_dig r/w 0 this bit companies with fan3_temp_sel select the temperature source for controlling fan3. 6 fan3_pwm_ freq_sel r/w 0 set this bit to select fan3 pwm output frequency. 0: 23.5 khz 1: 220 hz 5 fan3_up_t_en r /w 0 set 1 to force fan3 to full speed if any temperature over its high limit. 4 fan3_ interpolation_en r/w 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan3_jump_ high_en r/w 1 this register controls the fan3 duty movement when temperature over highest boundary. 0: the fan3 duty will increases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec1speed3 register. this bit only activates in duty mode. 2 fan3_jump_ low_en r/w 1 this register controls the fan3 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan3 duty will decreases with the slope selected by fan3_rate_sel register. 1: the fan3 duty will directly jumps to the value of sec2speed3 register. this bit only activates in duty mode. 1 - 0 fan3_temp_sel r /w 11 this registers companying with fan3_temp_sel_dig select the temperature source for controlling fan3. the following value is comprised by {fan3_temp_sel_dig, fan3_temp_sel} 000: fan3 follows peci temperature (cr7eh) 001: fan3 follows temperature 1 (cr72h). 010: fan3 follows temperature 2 (cr74h). 011: fan3 follows temperature 3 (cr76h). 100: fan3 follows ibex/tsi cpu temperature (cr7ah) 101: fan3 follows ibex pch temperature (cr7bh). 110: fan3 follows ibex m ch temperature (cr7ch). 111: fan3 follows ibex maxi mum temperature (cr7dh). otherwise: reserved.
finte k feature integration technology inc. dec, 2010 v0.21p 91 f71869e 6.6.83 tsi temperature 0 ? index e0h bit name r/w default description tsi_temp0 r /w - this is the amd tsi reading if amd tsi enable. and will be highest temperature am ong cpu, mch and pch if intel temperature interface enable. the ra nge is 0~255?c. to access this byte, mch_bank_sel must set to ?0?. 7-0 smb_data0 r /w 8?h00 this byte is used as multi-purpose: 5. the received data of receive protocol. 6. the first received byte of read word protocol. 7. the 10 th received byte of read block protocol. 8. the sent data for send byte protocol and write byte protocol. 9. the first send byte for write word protocol. 10. the first send byte for write block protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.84 tsi temperature 1 ? index e1h bit name r/w default description tsi_temp1 r - this is the high byte of intel te mperature interfac e pch reading. the range is 0~255?c. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data1 r /w 8?h00 this byte is used as multi-purpose: 1. the second received byte of read word protocol. 2. the 11 th received byte of read block protocol. 3. the second send byte for write word protocol. 4. the second send byte fo r write block protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.85 tsi temperature 2 low byte ? index e2h bit name r/w default description 7-0 tsi_temp2_lo r - this is the low byte of intel temperature interface cpu reading. the reading is the fraction part of cpu temperature. bit 0 indicates the error status. 0: no error. 1: error code. to access this byte, mch_ban k_sel should be set to ?0?.
finte k feature integration technology inc. dec, 2010 v0.21p 92 f71869e smb_data2 r /w 8?h00 this is the 12 th byte of the block read protocol. this byte is also used as the 3rd byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.86 tsi temperature 2 high byte ? index e3h bit name r/w default description tsi_temp2_hi r - this is the high byte of intel tem perature interface cpu reading. the reading is the decimal part of cpu temperature. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data3 r /w 8?h00 this is the 13 th byte of the block read protocol. this byte is also used as the 4t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.87 tsi temperature 3 ? index e4h bit name r/w default description tsi_temp3 r - this is the high byte of intel te mperature interfac e mch reading. the range is 0~255?c. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data4 r /w 8?h00 this is the 14 th byte of the block read protocol. this byte is also used as the 5t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.88 tsi temperature 4 ? index e5h bit name r/w default description tsi_temp4 r - this is the high byte of intel te mperature interface dimm0 reading. the range is 0~255?c. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data5 r /w 8?h00 this is the 15 th byte of the block read protocol. this byte is also used as the 6t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.89 tsi temperature 5 ? index e6h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 93 f71869e tsi_temp5 r - this is the high byte of intel te mperature interface dimm1 reading. the range is 0~255?c. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data6 r /w 8?h00 this is the 16 th byte of the block read protocol. this byte is also used as the 7t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.90 tsi temperature 6 ? index e7h bit name r/w default description tsi_temp6 r - this is the high byte of intel te mperature interface dimm2 reading. the range is 0~255?c. to access this byte, mch_ban k_sel should be set to ?0?. 7-0 smb_data7 r /w 8?h00 this is the 17 th byte of the block read protocol. this byte is also used as the 8t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.91 tsi temperature 7 ? index e8h bit name r/w default description tsi_temp7 r - this is the high byte of intel te mperature interface dimm3 reading. the range is 0~255?c. the above 9 bytes could also be used as the read data of block read protocol if the tsi is disable or pending. 7-0 smb_data8 r /w 8?h00 this is the 18 th byte of the block read protocol. this byte is also used as the 9t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.92 smb data buffer 9 ? index e9h bit name r/w default description 7-0 smb_data9 r/w ffh this is the 18 th byte of the block read protocol. this byte is also used as the 9t h byte of block write protocol. to access this byte, mch_ban k_sel should be set to ?1?. 6.6.93 block write count register ? index ech bit name r/w default description 7 mch_bank_sel r /w 0 this bit is used to select the register in index e0h to e9h. set ?0? to read the temperature bank and ?1? to access the data bank. 6 reserved - 0 reserved
finte k feature integration technology inc. dec, 2010 v0.21p 94 f71869e 5-0 block_wr_cnt r/w 0 use the register to specify the byte count of block write protocol. support up to 10 bytes. 6.6.94 smb command byte/tsi command byte ? index edh bit name r/w default description 7 - 0 smb_cmd/tsi_cmd r /w 0/1 there are actual two bytes for this index. tsi_cmd_prog select which byte to be programmed: 0: smb_cmd, which is the command code for write byte/word, read byte/word, block write/read and process call protocol. 1: tsi_cmd, which is the command code for intel temperature interface block read protocol and t he data byte for amd tsi send byte protocol. 6.6.95 smb status ? index eeh bit name r/w default description 7 tsi_pending r /w 0 set 1 to pending auto tsi accessing. (in amd model, auto accessing will issue a send-byte followed a re ceive-byte; in intel model, auto accessing will issue a block read). to use the tsi_scl/tsi_sda as a smbus master, set this bit to ?1? first. 6 tsi_cmd_prog r /w 0 set 1 to program tsi_cmd. 5 proc_kill r /w 0 kill the current smbus tran sfer and return the stat e machine to idle. it will set an fail status if the cu rrent transfer is not completed. 4 fail_sts r 0 this is set when proc_ki ll kill a un-completed transfer. it will be auto cleared by next smbus transfer. 3 smb_abt_err r 0 this is the arbitration lost status if a smbus command is issued. auto cleared by next smbus command. 2 smb_to_err r 0 this is the timeout status if a smbus command is issued. auto cleared by next smbus command. 1 smb_nac_err r 0 this is the nack error status if a smbus command is issued. auto cleared by next smbus command. 0 smb_ready r 1 0: a smbus transfer is in process. 1: ready for next smbus command. 6.6.96 smb protocol select ? index efh bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 95 f71869e 7 smb_start w 0 write ?1? to trigger a smbus transfer with the protocol specified by smb_protocol. 6-4 reserved - - reserved. 3 - 0 smb_protocol r /w 0 select what protocol if a smbus transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: reserved. 0101b: block write. 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: reserved 1101b: block read. 1111b: reserved otherwise: reserved.
finte k feature integration technology inc. dec, 2010 v0.21p 96 f71869e 6.7 kbc registers (cr05) 6.7.1 kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. 6.7.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc command port address. the address of data port is command port address + 4; 6.7.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc command port address. the address of data port is command port address + 4. 6.7.4 kbc irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selkirq r/w 1h select the irq channel for keyboard interrupt. 6.7.5 mouse irq channel select register ? index 72h bit name r/w default description 7-4 reserved - - reserved. 3-0 selmirq r/w ch select the irq channel for ps/2 mouse interrupt. 6.7.6 auto swap register ? index feh (powered by vbat) bit name r/w default description 7 auto_det_en r/w 0 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. 6-5 reserved - - reserved. 4 kb_mo_swap r/w 0 0: keyboard/mouse not swap. 1: keyboard/mouse swap. this bit is set/clear by hardware if auto_det_en is set to ?1?. users could also program this bit manually. 3-0 reserved - 1h reserved
finte k feature integration technology inc. dec, 2010 v0.21p 97 f71869e 6.8 gpio registers (cr06) 6.8.1 gpio device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 gpio_en r/w 0 0: disable gpio i/o port. 1: enable gpio i/o port. 6.8.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of gpio index/data port address. the index port is base_addr[15:2] + 5 and the data port is base_addr[15:2] + 6. 6.8.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of gpio index/data port address. the index port is base_addr[15:2] + 5 and the data port is base_addr[15:2] + 6. 6.8.4 gpirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selgpirq r/w 0h select the irq channel for gpio interrupt. 6.8.5 gpio0 output enable register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 gpio05_oe r/w 0 0: gpio05 is in input mode. 1: gpio05 is in output mode. 4 gpio04_oe r/w 0 0: gpio04 is in input mode. 1: gpio04 is in output mode. 3 gpio03_oe r/w 0 0: gpio03 is in input mode. 1: gpio03 is in output mode. 2 gpio02_oe r/w 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. 1 gpio01_oe r/w 0 0: gpio01 is in input mode. 1: gpio01 is in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 98 f71869e 0 gpio00_oe r/w 0 0: gpio00 is in input mode. 1: gpio00 is in output mode. 6.8.6 gpio0 output data register ? index f1h bit name r/w default description 7-6 reserved - - reserved. 5 gpio05_val r/w 1 0: gpio05 outputs 0 when in output mode. 1: gpio05 outputs 1 when in output mode. 4 gpio04_val r/w 1 0: gpio04 outputs 0 when in output mode. 1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 gpio01_val r/w 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. 0 gpio00_val r/w 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. 6.8.7 gpio pin status register ? index f2h bit name r/w default description 7-6 reserved - - reserved. 5 gpio05_in r - the pin status of 3vsbsw/gpio05 4 gpio04_in r - the pin status of slotocc#/gpio04 3 gpio03_in r - the pin status of timing1/gpio03 2 gpio02_in r - the pin status of timing2/gpio02 1 gpio01_in r - the pin status of timing4/gpio01 0 gpio00_in r - the pin status of timing3/gpio00 6.8.8 gpio drive enable register ? index f3h bit name r/w default description 7 reserved - - reserved. 5 gpio05_drv_en r/w 0 0: gpio05 is open drain in output mode. 1: gpio05 is push pull in output mode. 4 gpio04_drv_en r/w 0 0: gpio04 is open drain in output mode. 1: gpio04 is push pull in output mode. 3 gpio03_drv_en r/w 0 0: gpio03 is open drain in output mode. 1: gpio03 is push pull in output mode. 2 gpio02_drv_en r/w 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 99 f71869e 1 gpio01_drv_en r/w 0 0: gpio01 is open drain in output mode. 1: gpio01 is push pull in output mode. 0 gpio00_drv_en r/w 0 0: gpio00 is open drain in output mode. 1: gpio00 is push pull in output mode. 6.8.9 gpio1 output enable register ? index e0h bit name r/w default description 7 gpio17_oe r/w 0 0: gpio17 is in input mode. 1: gpio17 is in output mode. 6 gpio16_oe r/w 0 0: gpio16 is in input mode. 1: gpio16 is in output mode. 5 gpio15_oe r/w 0 0: gpio15 is in input mode. 1: gpio15 is in output mode. 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. 6.8.10 gpio1 output data register ? index e1h bit name r/w default description 7 gpio17_val r/w 1 0: gpio17 outputs 0 when in output mode. 1: gpio17 outputs1 when in output mode. 6 gpio16_val r/w 1 0: gpio16 outputs 0 when in output mode. 1: gpio16 outputs1 when in output mode. 5 gpio15_val r/w 1 0: gpio15 outputs 0 when in output mode. 1: gpio15 outputs 1 when in output mode. 4 gpio14_val r/w 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 100 f71869e 6.8.11 gpio1 pin status register ? index e2h bit name r/w default description 7 gpio17_in r - the pin status of cpu_pwrgd/gpio17. 6 gpio16_in r - the pin status of led_vcc/gpio16. 5 gpio15_in r - the pin status of led_vsb/alert#/gpio15. 4 gpio14_in r - the pin status of wdtrst#/gpio14. 3 gpio13_in r - the pin status of beep/gpio13. 2 gpio12_in r - the pin stat us of rstcon#/gpio12. 1 gpio11_in r - the pin status of pci_rst5#/gpio11. 0 gpio10_in r - the pin status of pci_rst4#/gpio10. 6.8.12 gpio1 drive enable register ? index e3h bit name r/w default description 7 gpio17_drv_en r/w 0 0: gpio17 is open drain in output mode. 1: gpio17 is push pull in output mode. 6 gpio16_drv_en r/w 0 0: gpio16 is open drain in output mode. 1: gpio16 is push pull in output mode. 5 gpio15_drv_en r/w 0 0: gpio15 is open drain in output mode. 1: gpio15 is push pull in output mode. 4 gpio14_drv_en r/w 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. 6.8.13 gpio1 pme enable register ? index e4h bit name r/w default description 7 gpio17_pme_en r/w 0 when gpio17_event_sts is 1 and gpio17_pme_en is set to 1, a gpio pme event will be generated. 6 gpio16_pme_en r/w 0 when gpio16_event_sts is 1 and gpio16_pme_en is set to 1, a gpio pme event will be generated. 5 gpio15_pme_en r/w 0 when gpio15_event_sts is 1 and gpio15_pme_en is set to 1, a gpio pme event will be generated. 4 gpio14_pme_en r/w 0 when gpio14_event_sts is 1 and gpio14_pme_en is set to 1, a gpio pme event will be generated. 3 gpio13_pme_en r/w 0 when gpio13_event_sts is 1 and gpio13_pme_en is set to 1, a gpio pme event will be generated.
finte k feature integration technology inc. dec, 2010 v0.21p 101 f71869e 2 gpio12_pme_en r/w 0 when gpio12_event_sts is 1 and gpio12_pme_en is set to 1, a gpio pme event will be generated. 1 gpio11_pme_en r/w 0 when gpio11_event_sts is 1 and gp io11_pme_en is set to 1, a gpio pme event will be generated. 0 gpio10_pme_en r/w 0 when gpio10_event_sts is 1 and gpio10_pme_en is set to 1, a gpio pme event will be generated. 6.8.14 gpio1 input detection select register ? index e5h bit name r/w default description 7 gpio17_det_sel r/w 0 when gpio17 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 6 gpio16_det_sel r/w 0 when gpio16 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 5 gpio15_det_sel r/w 0 when gpio15 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 4 gpio14_det_sel r/w 0 when gpio14 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 3 gpio13_det_sel r/w 0 when gpio13 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 2 gpio12_det_sel r/w 0 when gpio12 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 1 gpio11_det_sel r/w 0 when gpio11 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 0 gpio10_det_sel r/w 0 when gpio10 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 6.8.15 gpio1 event status register ? index e6h bit name r/w default description 7 gpio17_ event_sts r/w 0 when gpio17 is in input mode and a gpio17 input is detected according to cre5[7], this bit will be set to 1. write a 1 to this bit will clear it to 0.
finte k feature integration technology inc. dec, 2010 v0.21p 102 f71869e 6 gpio16_ event_sts r/w 0 when gpio16 is in input mode and a gpio16 input is detected according to cre5[6], this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 gpio15_ event_sts r/w 0 when gpio15 is in input mode and a gpio15 input is detected according to cre5[5], this bit will be set to 1. write a 1 to this bit will clear it to 0. 4 gpio14_ event_sts r/w 0 when gpio14 is in input mode and a gpio14 input is detected according to cre5[4], this bit will be set to 1. write a 1 to this bit will clear it to 0. 3 gpio13_ event_sts r/w 0 when gpio13 is in input mode and a gpio13 input is detected according to cre5[3], this bit will be set to 1. write a 1 to this bit will clear it to 0. 2 gpio12_ event_sts r/w 0 when gpio12 is in input mode and a gpio12 input is detected according to cre5[2], this bit will be set to 1. write a 1 to this bit will clear it to 0. 1 gpio11_ event_sts r/w 0 when gpio11 is in input mode and a gpio11 input is detected according to cre5[1], this bit will be set to 1. write a 1 to this bit will clear it to 0. 0 gpio10_ event_sts r/w 0 when gpio10 is in input mode and a gpio10 input is detected according to cre5[0], this bit will be set to 1. write a 1 to this bit will clear it to 0. 6.8.16 gpio2 output enable register ? index d0h bit name r/w default description 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio25 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. 6.8.17 gpio2 output data register ? index d1h bit name r/w default description 7 gpio27_val r/w 1 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs 1 when in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 103 f71869e 6 gpio26_val r/w 1 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs 1 when in output mode. 5 gpio25_val r/w 1 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode. 4 gpio24_val r/w 1 0: gpio24 outputs 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 gpio23_val r/w 1 0: gpio23 outputs 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 1 0: gpio22 outputs 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 1 0: gpio21 outputs 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 1 0: gpio20 outputs 0 when in output mode. 1: gpio20 outputs 1 when in output mode. 6.8.18 gpio2 pin status register ? index d2h bit name r/w default description 7 gpio27_in r - the pin status of sin2/gpio27. 6 gpio26_in r - the pin status of sout2/gpio26. 5 gpio25_in r - the pin status of dsr2#/gpio25. 4 gpio24_in r - the pin status of rts2#/gpio24. 3 gpio23_in r - the pin status of dtr2#/gpio23. 2 gpio22_in r - the pin status of cts2#/gpio22. 1 gpio21_in r - the pin status of ri2#/gpio21. 0 gpio20_in r - the pin status of dcd2#/gpio20. 6.8.19 gpio2 drive enable register ? index d3h bit name r/w default description 7 gpio27_drv_en r/w 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode. 6 gpio26_drv_en r/w 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 0 0: gpio24 is open drain in output mode. 1: gpio24 is push pull in output mode. 3 gpio23_drv_en r/w 0 0: gpio23 is open drain in output mode. 1: gpio23 is push pull in output mode. 2 gpio22_drv_en r/w 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 104 f71869e 0 gpio20_drv_en r/w 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode. 6.8.20 gpio3 output enable register ? index c0h bit name r/w default description 7 gpio37_oe r/w 0 0: gpio37 is in input mode. 1: gpio37 is in output mode. (open-drain). 6 gpio36_oe r/w 0 0: gpio36 is in input mode. 1: gpio35 is in output mode. (open-drain). 5 gpio35_oe r/w 0 0: gpio35 is in input mode. 1: gpio35 is in output mode. (open-drain). 4 gpio34_oe r/w 0 0: gpio34 is in input mode. 1: gpio34 is in output mode. (open-drain). 3 gpio33_oe r/w 0 0: gpio33 is in input mode. 1: gpio33 is in output mode. (open-drain). 2 gpio32_oe r/w 0 0: gpio32 is in input mode. 1: gpio32 is in output mode. (open-drain). 1 gpio31_oe r/w 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. (open-drain). 0 gpio30_oe r/w 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. (open-drain). 6.8.21 gpio3 output data register ? index c1h bit name r/w default description 7 gpio37_val r/w 1 0: gpio37 outputs 0 when in output mode. 1: gpio37 outputs 1 when in output mode. 6 gpio36_val r/w 1 0: gpio36 outputs 0 when in output mode. 1: gpio36 outputs 1 when in output mode. 5 gpio35_val r/w 1 0: gpio35 outputs 0 when in output mode. 1: gpio35 outputs 1 when in output mode. 4 gpio34_val r/w 1 0: gpio34 outputs 0 when in output mode. 1: gpio34 outputs 1 when in output mode. 3 gpio33_val r/w 1 0: gpio33 outputs 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w 1 0: gpio32 outputs 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w 1 0: gpio31 outputs 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w 1 0: gpio30 outputs 0 when in output mode. 1: gpio30 outputs 1 when in output mode. 6.8.22 gpio3 pin status register ? index c2h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 105 f71869e 7 gpio37_in r - the pin status of wgate#/gpio37. 6 gpio36_in r - the pin status of hdsel#/gpio36. 5 gpio35_in r - the pin status of step#/gpio35. 4 gpio34_in r - the pin status of dir#/gpio34. 3 gpio33_in r - the pin status of wdata#/gpio3. 2 gpio32_in r - the pin status of drva#/gpio32. 1 gpio31_in r - the pin status of moa#/gpio31. 0 gpio30_in r - the pin status of densel#/gpio30. 6.8.23 gpio4 output enable register ? index b0h bit name r/w default description 7 gpio47_oe r/w 0 0: gpio47 is in input mode. 1: gpio47 is in output mode. 6 gpio46_oe r/w 0 0: gpio46 is in input mode. 1: gpio46 is in output mode. 5 gpio45_oe r/w 0 0: gpio45 is in input mode. 1: gpio45 is in output mode. 4 gpio44_oe r/w 0 0: gpio44 is in input mode. 1: gpio44 is in output mode. 3 gpio43_oe r/w 0 0: gpio43 is in input mode. 1: gpio43 is in output mode. 2 gpio42_oe r/w 0 0: gpio42 is in input mode. 1: gpio42 is in output mode. 1 gpio41_oe r/w 0 0: gpio41 is in input mode. 1: gpio41 is in output mode. 0 gpio40_oe r/w 0 0: gpio40 is in input mode. 1: gpio40 is in output mode. 6.8.24 gpio4 output data register ? index b1h bit name r/w default description 7 gpio47_val r/w 1 0: gpio47 outputs 0 when in output mode. 1: gpio47 outputs 1 when in output mode. 6 gpio46_val r/w 1 0: gpio46 outputs 0 when in output mode. 1: gpio46 outputs 1 when in output mode. 5 gpio45_val r/w 1 0: gpio45 outputs 0 when in output mode. 1: gpio45 outputs 1 when in output mode. 4 gpio44_val r/w 1 0: gpio44 outputs 0 when in output mode. 1: gpio44 outputs 1 when in output mode. 3 gpio43_val r/w 1 0: gpio43 outputs 0 when in output mode. 1: gpio43 outputs 1 when in output mode. 2 gpio42_val r/w 1 0: gpio42 outputs 0 when in output mode. 1: gpio42 outputs 1 when in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 106 f71869e 1 gpio41_val r/w 1 0: gpio41 outputs 0 when in output mode. 1: gpio41 outputs 1 when in output mode. 0 gpio40_val r/w 1 0: gpio40 outputs 0 when in output mode. 1: gpio40 outputs 1 when in output mode. 6.8.25 gpio4 pin status register ? index b2h bit name r/w default description 7 gpio47_in r - the pin status of ps_on#/gpio47. 6 gpio46_in r - the pin status of pwsout#/gpio46 5 gpio45_in r - the pin status of pwsin#/gpio45 4 gpio44_in r - the pin status of atxpg_in/gpio44 3 gpio43_in r - the pin status of irrx/gpio43. 2 gpio42_in r - the pin status of irtx/gpio42. 1 gpio41_in r - the pin status of fanctl3/gpio41. 0 gpio40_in r - the pin status of fanin3/gpio40. 6.8.26 gpio4 drive enable register ? index b3h bit name r/w default description 7-4 reserved - - reserved 3 gpio43_drv_en r/w 0 0: gpio43 is open drain in output mode. 1: gpio43 is push pull in output mode. 2 gpio42_drv_en r/w 0 0: gpio42 is open drain in output mode. 1: gpio42 is push pull in output mode. 1 gpio41_drv_en r/w 0 0: gpio41 is open drain in output mode. 1: gpio41 is push pull in output mode. 0 gpio40_drv_en r/w 0 0: gpio40 is open drain in output mode. 1: gpio40 is push pull in output mode. 6.8.27 gpio4 pme enable register ? index b4h bit name r/w default description 7-4 reserved - - reserved 3 gpio43_pme_en r/w 0 when gpio43_event_sts is 1 and gpio43_pme_en is set to 1, a gpio pme event will be generated. 2 gpio42_pme_en r/w 0 when gpio42_event_sts is 1 and gpio42_pme_en is set to 1, a gpio pme event will be generated. 1 gpio41_pme_en r/w 0 when gpio41_event_sts is 1 and gpio41_pme_en is set to 1, a gpio pme event will be generated. 0 gpio40_pme_en r/w 0 when gpio40_event_sts is 1 and gpio40_pme_en is set to 1, a gpio pme event will be generated.
finte k feature integration technology inc. dec, 2010 v0.21p 107 f71869e 6.8.28 gpio4 input detection select register ? index b5h bit name r/w default description 7-4 reserved - - reserved 3 gpio43_det_sel r/w 0 when gpio43 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 2 gpio42_det_sel r/w 0 when gpio42 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 1 gpio41_det_sel r/w 0 when gpio41 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 0 gpio40_det_sel r/w 0 when gpio40 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 6.8.29 gpio4 event status register ? index b6h bit name r/w default description 7-4 reserved - - reserved 3 gpio43_ event_sts r/w - when gpio43 is in input mode and a gpio43 input is detected according to crb5[3], this bit will be set to 1. write a 1 to this bit will clear it to 0. 2 gpio42_ event_sts r/w - when gpio42 is in input mode and a gpio42 input is detected according to crb5[2], this bit will be set to 1. write a 1 to this bit will clear it to 0. 1 gpio41_ event_sts r/w - when gpio41 is in input mode and a gpio41 input is detected according to crb5[1], this bit will be set to 1. write a 1 to this bit will clear it to 0. 0 gpio40_ event_sts r/w - when gpio40 is in input mode and a gpio40 input is detected according to crb5[0], this bit will be set to 1. write a 1 to this bit will clear it to 0. 6.8.30 gpio5 output enable register ? index a0h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_oe r/w 0 0: gpio54 is in input mode. 1: gpio54 is in output mode. 3 gpio53_oe r/w 0 0: gpio53 is in input mode. 1: gpio53 is in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 108 f71869e 2 gpio52_oe r/w 0 0: gpio52 is in input mode. 1: gpio52 is in output mode. 1 gpio51_oe r/w 0 0: gpio51 is in input mode. 1: gpio51 is in output mode. 0 gpio50_oe r/w 0 0: gpio50 is in input mode. 1: gpio50 is in output mode. 6.8.31 gpio5 output data register ? index a1h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_val r/w 1 0: gpio54 outputs 0 when in output mode. 1: gpio54 outputs 1 when in output mode. 3 gpio53_val r/w 1 0: gpio53 outputs 0 when in output mode. 1: gpio53 outputs 1 when in output mode. 2 gpio52_val r/w 1 0: gpio52 outputs 0 when in output mode. 1: gpio52 outputs 1 when in output mode. 1 gpio51_val r/w 1 0: gpio51 outputs 0 when in output mode. 1: gpio51 outputs 1 when in output mode. 0 gpio50_val r/w 1 0: gpio50 outputs 0 when in output mode. 1: gpio50 outputs 1 when in output mode. 6.8.32 gpio5 pin status register ? index a2h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_in r - the pin status of dskchg#/gpio54. 3 gpio53_in r - the pin status of wpt#/gpio53. 2 gpio52_in r - the pin status of index#/gpio52. 1 gpio51_in r - the pin status of trk0#/gpio51. 0 gpio50_in r - the pin status of rddata#/gpio50. 6.8.33 gpio5 drive enable register ? index a3h bit name r/w default description 7-5 reserved - - reserved. 4 gpio54_drv_en r/w 0 0: gpio54 is open drain in output mode. 1: gpio54 is push pull in output mode. 3 gpio53_drv_en r/w 0 0: gpio53 is open drain in output mode. 1: gpio53 is push pull in output mode. 2 gpio52_drv_en r/w 0 0: gpio52 is open drain in output mode. 1: gpio52 is push pull in output mode. 1 gpio51_drv_en r/w 0 0: gpio51 is open drain in output mode. 1: gpio51 is push pull in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 109 f71869e 0 gpio50_drv_en r/w 0 0: gpio50 is open drain in output mode. 1: gpio50 is push pull in output mode. 6.8.34 gpio6 output enable register ? index 90h bit name r/w default description 7-6 reserved - - reserved. 5 gpio65_oe r/w 0 0: gpio65 is in input mode. 1: gpio65 is in output mode. 4 gpio64_oe r/w 0 0: gpio64 is in input mode. 1: gpio64 is in output mode. 3 gpio63_oe r/w 0 0: gpio63 is in input mode. 1: gpio63 is in output mode. 2-0 reserved r/w 0 reserved 6.8.35 gpio6 output data register ? index 91h bit name r/w default description 7-6 reserved - - reserved. 5 gpio65_val r/w 1 0: gpio65 outputs 0 when in output mode. 1: gpio65 outputs 1 when in output mode. 4 gpio64_val r/w 1 0: gpio64 outputs 0 when in output mode. 1: gpio64 outputs 1 when in output mode. 3 gpio63_val r/w 1 0: gpio63 outputs 0 when in output mode. 1: gpio63 outputs 1 when in output mode. 2-0 reserved r/w 1 reserved 6.8.36 gpio6 pin status register ? index 92h bit name r/w default description 7-6 reserved - - reserved. 5 gpio65_in r - the pin status of bit_sel_out3/gpio65. 4 gpio64_in r - the pin status of bit_sel_out2/gpio64. 3 gpio63_in r - the pin status of bit_sel_out1/gpio63. 2-0 reserved r - reserved 6.8.37 gpio6 drive enable register ? index 93h bit name r/w default description 7-6 reserved - - reserved. 5 gpio65_drv_en r/w 0 0: gpio65 is open drain in output mode. 1: gpio65 is push pull in output mode. 4 gpio64_drv_en r/w 0 0: gpio64 is open drain in output mode. 1: gpio64 is push pull in output mode.
finte k feature integration technology inc. dec, 2010 v0.21p 110 f71869e 3 gpio63_drv_en r/w 0 0: gpio63 is open drain in output mode. 1: gpio63 is push pull in output mode. 2-0 reserved r/w 0 reserved
finte k feature integration technology inc. dec, 2010 v0.21p 111 f71869e 6.9 watch dog timer registers (cr07) 6.9.1 configuration register ? index f0h (offset 00h) (* cleared by slotocc# and watch dog timeout) bit name r/w default description 7 wdout_en r/w - this bit is decided by rts1# power-on trapping. if this bit is set to 1 and watchd og timeout event occurs, wdtrst# output is enabled. 6-1 reserved - - reserved 0 wd_rst_en r/w 1 0: disable wdt to reset the vid register marked with *. 1: enable wdt to reset the vi d register marked with *. 6.9.2 serial key data register 1 ? index f2h (offset 02h) bit name r/w default description 7 reserved - - reserved 6 key_ok r 1 this bit is 1 represents that t he serial key is entered correctly. 5-0 reserved - - reserved 6.9.3 serial key data register 2 ? index f3h (offset 03h) bit name r/w default description 7-0 key_data r/w f3h write serial data to this register co rrectly, the key_ok bit will be set to 1. hence, users are able to wr ite key protected registers. the sequence to enable key_ok is 0x 32, 0x5d, 0x42, 0xac. when key_ok is set, write this r egister 0x35 will clear key_ok. 6.9.4 reserved ? index f4h (offset 04h) bit name r/w default description 7-0 reserved - - reserved 6.9.5 watchdog timer configuration register 1 ? index f5h (offset 05h) bit name r/w default description 7 wdt_clk_sel r 0 select the wdt clock source. 0: the clock source is from clkin. (powered by vdd and is accurate)\ 1: the clock source is from in ternal 500khz (powered by vsb3v and 20% tolerance).
finte k feature integration technology inc. dec, 2010 v0.21p 112 f71869e 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w - this bit is decided by rts1# power-on trapping. if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit. 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1:0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 750 us 1: 18 ms 2: 93 ms 3: 3.75 sec 6.9.6 watchdog timer configuration register 2 ? index f6h (offset 06h) bit name r/w default description 7:0 wd_time r/w 0a time of watchdog timer 6.9.7 wdt pme register ? index f7h (offset 07h) bit name r/w default description 7 wdt_pme r 0 wdt pme real time status. 6 wdt_pme_en r/w 0 0: disable wdt pme. 1: enable wdt pme. 6 wdt_pme_st r/w 0 0: no wdt pme occurred. 1: wdt pme occurred. the wdt pme is occurred one unit before wdt timeout. 4-1 reserved r 0 reserved 0 cpu_change r/w c - this bit will be set at slotocc# rising edge. internal 1us de-bounce circuit is implemented. write ?1? to th is bit will clear the status.(this bit is powered by vbat.)
finte k feature integration technology inc. dec, 2010 v0.21p 113 f71869e 6.10 pme, acpi, and eup powe r saving registers (cr0a) 6.10.1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. 6.10.2 eup enable register ? index e0h bit name r/w default description 7 eup_en r/w 0 0 : disable eup function 1: enable eup function 6-2 reserved - - reserved 1 ring_pme_en r/w 0 ring1 pme event enable. 0: disable ring1 pme event. 1: enable ring1 pme event, when ring1 falling edge detect 0 ring_psout_en r/w 0 ring1 psout event enable. 0: disable ring1 psout event. 1: enable ring1 psout event, when ring1 falling edge detect 6.10.3 eup control register ? index e1h bit name r/w default description 7-6 boot_mode r/w 11 write these two bits to select boot mode for always off/ always on/ keep last state. 00:always off 11:support always on and keep last state 10:reserved 01:reserved 5 s3_ ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low when s3 state. else if set to ?1? ctrl_1 will output high when s3 state. 4 s3 _ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low when s3 state. else if set to ?1? ctrl_0 will output high when s3 state. 3 s5 _ctrl_1_dis r/w 1 if clear to ?0? ctrl_1 will output low when s5 state. else if set to ?1? ctrl_1 will output high when s5 state. 2 s5 _ctrl_0_dis r/w 1 if clear to ?0? ctrl_0 will output low when s5 state. else if set to ?1? ctrl_0 will output high when s5 state. 1 ac_ ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low w hen after ac lost. else if set to ?1? ctrl_1 will output high when after ac lost. 0 ac_ ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low w hen after ac lost. else if set to ?1? ctrl_0 will output high when after ac lost. 6.10.4 eup control register ? index e2h bit name r/w default description 7 ac_lost r - this bit is ac lost status and writes 1 to this bit will clear it.
finte k feature integration technology inc. dec, 2010 v0.21p 114 f71869e 6 reserved r/w 0 reserved 5 vsb_ctrl_en[1] r/w 1?b0 0: disable eup ctrl_1 assert rsmrst low 1: enable eup ctrl_1 assert rsmrst low 4 vsb_ctrl_en[0] r/w 1?b0 0: disable eup ctrl_0 assert rsmrst low 1: enable eup ctrl_0 assert rsmrst low 3 s5_det_s5# r/w 1 device into s5 state will check s5# signal and vcc_in pin status, but when user clear this bit to 0. device into s5 state will not check s5# become low. 2 s5_det_vcc r/w 1 device into s5 state will check s5# signal and vcc_in pin status, but when user clear this bit to 0. device into s5 state will not check vcc_in become low. 1 rsmrst_det_5v_ n r/w 0 device detects vsb5v power ok (4.4v) and vsb3v_in become high, and after ~50ms de-bounce time rsmrst will become high. but when user set this bit to 1. rsmrst will not check vsb5v power ok. 0 reserved r - reserved 6.10.5 eup psin deb-register ? index e3h bit name r/w default description 7-0 ps_deb_time r/w 0x13 ps_in pin input de-bounce time default is ~15msec 6.10.6 eup rsmrst deb-register ? index e4h bit name r/w default description 7-0 rsmrst_deb_tim e r/w 0x09 rsmrst internal de-bounce time default is ~10msec 6.10.7 eup psout deb-register ? index e5h bit name r/w default description 7-0 ps_out_pulse_w r/w 0xc7 ps_out_out output pulse width default is ~150msec low pulse 6.10.8 eup pson deb-register ? index e6h bit name r/w default description 7-0 ps_on_deb_time r/w 0x09 pson_in pin input de-bounce time default is 10msec 6.10.9 eup s5 deb-register ? index e7h bit name r/w default description 7-0 s5_deb_time r/w 0x63 s5# pin input de-bounce time default is ~5sec. the unit of this byte is ~50ms. 6.10.10 wakeup enable register ? index e8h bit name r/w default description 7 ri2_wakeup_en r/w 0 set this bit to enable ri2# event to wakeup system. 6 reserved r/w - reserved 5 ri1_wakeup_en r/w 0 set this bit to enable ri1# event to wakeup system. 4 ring_wakeup_en r/w 1 set this bit to enable event_in# event to wakeup system.
finte k feature integration technology inc. dec, 2010 v0.21p 115 f71869e 3 gp_wakeup_en r/w 0 set this bit to enable gpio event to wakeup system. 2 tmout_wakeup_en r/w 0 set this bit to enable timeout event to wakeup system. 1 mo_wakeup_en r/w 0 set this bit to enable mouse event to wakeup system. 0 kb_wakeup_en r/w 0 set this bit to enable keyboard event to wakeup system. 6.10.11 eup wdt control register ? index edh bit name r/w default description 7-5 reserved r - reserved 4 eup_wdtmout r - eup wdt timeout status. 3-2 reserved r - reserved 1 wd_unit r/w 0 eup wdt unit. it is the time unit of eup_wd_time. 0: 1sec. 1: 60 sec. 0 wd_en r/w 0 set ?1? to enable eup wdt. au to clear if timeout occurs. 6.10.12 eup wdt timer ? index eeh bit name r/w default description 7-1 reserved - - reserved 0 eup_wd_time r/w 0 time of eup watchdog timer. 6.10.13 pme event enable register 1 ? index f0h bit name r/w default description 7 wdt_pme_en r/w 0 wdt pme event enable. 0: disable wdt pme event. 1: enable wdt pme event. 6 mo_pme_en r/w 0 mouse pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 5 kb_pme_en r/w 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 4 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 3 prt_pme_en r/w 0 parallel port pme event enable. 0: disable parallel port pme event. 1: enable parallel port pme event. 2 ur2_pme_en r/w 0 uart 2 pme event enable. 0: disable uart 2 pme event. 1: enable uart 2 pme event. 1 ur1_pme_en r/w 0 uart 1 pme event enable. 0: disable uart 1 pme event. 1: enable uart 1 pme event.
finte k feature integration technology inc. dec, 2010 v0.21p 116 f71869e 0 fdc_pme_en r/w 0 fdc pme event enable. 0: disable fdc pme event. 1: enable fdc pme event. 6.10.14 pme event status register ? index f1h bit name r/w default description 7 wdt_pme_st r/w - wdt pme event status. 0: wdt has no pme event. 1: wdt has a pme event to assert. write 1 to clear to be ready for next pme event. 6 mo_pme_st r/w - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. write 1 to clear to be ready for next pme event. 5 kb_pme_st r/w - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 4 hm_pme_st r/w - hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 3 prt_pme_st r/w - parallel port pme event status. 0: parallel port has no pme event. 1: parallel port has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ur2_pme_st r/w - uart 2 pme event status. 0: uart 2 has no pme event. 1: uart 2 has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ur1_pme_st r/w - uart 1 pme event status. 0: uart 1 has no pme event. 1: uart 1 has a pme event to assert. write 1 to clear to be ready for next pme event. 0 fdc_pme_st r/w - fdc pme event status. 0: fdc has no pme event. 1: fdc has a pme event to assert. write 1 to clear to be ready for next pme event. 6.10.15 pme event enable register 2 ? index f2h bit name r/w default description 7-3 reserved - - reserved 2 ri2_pme_en r/w 0 ri2# pme event enable. 0: disable ri2# pme event. 1: enable ri2# pme event.
finte k feature integration technology inc. dec, 2010 v0.21p 117 f71869e 1 ri1_pme_en r/w 0 ri1# pme event enable. 0: disable ri1# pme event. 1: enable ri1# pme event. 0 gp_pme_en r/w 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. 6.10.16 pme event status register ? index f3h bit name r/w default description 7-4 reserved - - reserved 3 eup_pme_st r/w - eup pme event status. 0: eup has no pme event. 1: eup has a pme event to assert. write 1 to clear to be ready for next pme event. 2 ri2_pme_st r/w - ri2# pme event status. 0: ri2# has no pme event. 1: ri2# has a pme event to assert. write 1 to clear to be ready for next pme event. 1 ri1_pme_st r/w - ri1# pme event status. 0: ri1# has no pme event. 1: ri1# has a pme event to assert. write 1 to clear to be ready for next pme event. 0 gp_pme_st r/w - gpio pme event status. 0: gpio has no pme event. 1: gpio has a pme event to assert. write 1 to clear to be ready for next pme event. 6.10.17 keep last state select register ? index f4h bit name r/w default description 7 reserved - 0 reserved 6-5 reserved - 0 reserved 4 en_kbwakeup r/w 0 set one to enable keyboard wakeup event asserted via pwsout#. 3 en_mowakeup r/w 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : bypass mode. 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it 6.10.18 vddok delay register ? index f5h bit name r/w default description
finte k feature integration technology inc. dec, 2010 v0.21p 118 f71869e 7-6 pwrok_delay r/w 0 the additional pwrok delay. the unit is 75 ms. 00: no delay 01: 1x 10: 2x 11: 4x 5 rstcon_en r/w 0 0: rstcon# will assert via pwrok. 1: rstcon# will assert via pcirst4# and pcirst5#. 4-3 vdd_delay r/w 11 the pwrok delay timing from vdd3vok by followed setting. the unit is 75 ms. 00 : 1x 01 : 2x 10 : 3x 11 : 4x 2 vindb_en r/w 1 enable the pcir stin_n and atxpwgd de-bounce. 1 pcirst_db_en r/w 0 enable the lreset_n de-bounce. 0 reserved r/w 0 reserved 6.10.19 pcirst control register ? index f6h bit name r/w default description 7 s3_sel r/w 0 select the kbc s3 state. 0: enter s3 state when internal vdd3vok signal de-asserted. 1: enter s3 state when s3# is low or the ts3 register is set to 1. 6 pson_del_en r/w 0 0: pson# is the inverted of s3# signal. 1: pson# will sink low only if the time after the last turn-off elapse at least 4 seconds. 5 reserved - - reserved 4 pcirst5_gate r/w 1 write ?0? to this bit will force pcirst5# to sink low. 3 pcirst4_gate r/w 1 write ?0? to this bit will force pcirst4# to sink low. 2 pcirst3_gate r/w 1 write ?0? to this bit will force pcirst3# to sink low. 1 pcirst2_gate r/w 1 write ?0? to this bit will force pcirst2# to sink low. 0 pcirst1_gate r/w 1 write ?0? to this bit will fo rce pcirst1# to sink low. 6.10.20 power sequence control register ? index f7h bit name r/w default description 7 vdimm_s3_on r/w 1 0: timing_1 will low during s3 state. 1: timing_1 will be tri-state during s3 state. 6 vdda_s3_on r/w 0 0: timing_2 will low during s3 state. 1: timing_2 will be tri-state during s3 state. 5 vcore_s3_on r/w 0 0: timing_3 will low during s3 state. 1: timing_3 will be tri-state during s3 state. 4 vldt_s3_on r/w 0 0: timing_4 will low during s3 state. 1: timing_4 will be tri-state during s3 state. 3 wdt_pwrok_en r/w 0 set ?1? to enable wdtrst# assert from pwrok pin.
finte k feature integration technology inc. dec, 2010 v0.21p 119 f71869e 2 atxpg_sw_tri r/w 1 0: atxpgsw# will sink low in s5 state. 1: atxpgsw# will be tri-state in s5 state. 1 pwr_st2_tri r/w 1 0: st2 will sink low in s5 state. 1: st2 will be tri-state in s5 state. 0 reserved r/w 0 reserved 6.10.21 led vcc mode select register ? index f8h bit name r/w default description 7 led_invert r/w 0 0: default invert signal 1: invert disable 6 reserved - - reserved 5-4 led_vcc_ s5_mode r/w 0 select led_vcc mode in s5 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock. 3-2 led_vcc_ s3_mode r/w 0 select led_vcc mode in s3 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock. 1-0 led_vcc_ s0_mode r/w 0 select led_vcc mode in s0 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock. 6.10.22 led vsb mode select register ? index f9h bit name r/w default description 7-6 reserved - - reserved 5-4 led_vsb_ s5_mode r/w 0 select led_vsb mode in s5 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock. 3-2 led_vsb_ s3_mode r/w 0 select led_vsb mode in s3 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock. 1-0 led_vsb_ s0_mode r/w 0 select led_vsb mode in s0 state. 00: sink low. 01: tri-state. 10: 0.5hz clock. 11: 1hz clock.
finte k feature integration technology inc. dec, 2010 v0.21p 120 f71869e 6.10.23 ri de-bounce select register ? index feh bit name r/w default description 7-2 reserved - - reserved 1-0 ri_db_sel r/w 0 select ri de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms.
finte k feature integration technology inc. dec, 2010 v0.21p 121 f71869e 7. electrical characteristic 7.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under abso lute maximum ratings may adversely affect the life and reliability of the device 7.2 dc characteristics (ta = 0 c to 70 c, vcc = 3.3v 10%, vss = 0v) parameter sym. min. typ. max. unit conditions operating voltage vdd 3.0 3.3 3.6 v battery voltage vbat 2.4 3.3 3.6 v operating current icc 10 ma vcc=3.3v vbat=3.3v idle state current isty 5 ua vcc=3.3v vbat=3.3v battery current ibat 4 ua vcc=3.3v vbat=3.3v i/od 12st5v - ttl level and schmitt trigger bi-directional pin with 12 ma source-sink capability 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v hysteresis 0.5 v output low current iol +12 ma vol = 0.4v input high leakage ilih -1 +1 a input low leakage ilil -1 +1 a i/o 12 ? output pin with12ma sour ce-sink capability ,5v tolerance input low voltage vil 0.8 v vdd = 3.3 v input high voltage vih 2.0 v vdd = 3.3 v hysteresis 0.5 v output high current ioh 12 ma voh = 2.0 v input high leakage ilih -1 +1 a input low leakage ilil -1 +1 a in ts_5v ? ttl level input pin and schmitt trigger, 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v hysteresis 0.5 v input high leakage ilih +1 a input low leakage ilil -1 a
finte k feature integration technology inc. dec, 2010 v0.21p 122 f71869e 8. ordering information part number package type production flow F71869ED 128-lqfp (green package) commercial, 0 c to +70 c 9. package dimensions (128-lqfp) figure 19 128 pin lqfp package diagram
finte k feature integration technology inc. dec, 2010 v0.21p 123 f71869e please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw
finte k feature integration technology inc. dec, 2010 v0.21p 124 f71869e 10. application circuit densel# moa# index# drva# step# dir# wpt# rdata# wdata# wgate# tr k0# vcc3v dskchg# hdsel# pwok rsmrst# vsb3v r1 4.7k r5 4.7k rsmrst# and pwok pull-up ctrl0# lreset# tr k0# dsr2# rts2# dtr2# sin2 sout2 st1 & st2 pull-up st2 vsb3v r15 4.7k r16 4.7k st1 2 2 4 4 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 1 1 3 3 5 5 7 7 9 9 11 11 13 13 15 15 17 17 19 19 21 21 23 23 25 25 27 27 29 29 31 31 33 33 j1 header 17x2 5vsb_atx 1 2 c6 0.1u even_in# vsb3v index# r115 10r fanctl2 2e 4e tit le size document number rev date: sheet of F71869ED&fdd 2.0 feature integration technology inc. b 18 tuesday , december 21, 2010 fanctl3 kdat kclk md at mc lk pwok led_vcc cpu_pwrgd ovt# pwsin# pwsout# s3# pson# pcirst3# s5# atxpg_in pme# pcirst1# pcirst2# timing gpio vcc3v vsb3v r10 1k config 4e/2e vcc3v function pin hi net name lo wpt# s3 irrx irtx densel# sout1# dtr1# floppy conn. fanin1 r6 1k r4 1k r2 1k r3 1k r7 1k 26 vcc5v 22 wpt# rdata# trk0# index# dskchg# 124 121 vbat fan speed duty:40% fan speed duty:100% 52 fan40_100 fanctl1 drva# 1 2 c1 0.1u fanctl3 timing/gpio (place capacitor close to ic) step# vcc3v 1 2 c3 0.1uf pciclk fanctl2 sout1# 24 vcc3v vsb3v 1 2 c4 0.1u fanctl1 lad3 1 2 c2 0.1u vcc3v timing/gpio 1 2 c5 0.1u vbat (gnd close to ic) lad2 gpio timing dtr1# fanctl1 lad1 r9 1k moa# fanctl1 fanctl2 fanctl3 dskchg# hdsel# lad0 cts2# dtr1# cts1# ri1# dcd1# dir# sin1 sout1 dsr1# rts1# ri2# dcd2# linear fan linear fan pwm fan pwm fan pwm fan linear fan lframe# fanctl2 fanin2 pd7 ack# pd4 init# slin# pd5 pd6 pd0 stb# afd# err# pd3 pd2 pd1 atxpg_in serirq wgate# wdtrst# ldrq# r8 1k r12 1k peci ibx_clk led_vsb ibx_dat st2 st1 rstcon# peci_req# gpio64 ti mi n g_2 gpio65 ti mi n g_1 r11 1k ti mi n g_gpi o ctrl1# gpio63 ti mi n g_gpi o clk_24/48m kbrst# ga20 ti mi n g_3 ti mi n g_4 power-on trip ga20 r14 1k atx_pwrgdsw clk_24/48m wdtrst# kbrst# fanin3 fanctl3 vdda(vin3) vcore(vin1) vldt(vin2) slct rsmrst# d3+ d- pe copen# vref d1+ d2+ busy vd i mm(vi n 4) vin5 vin6 rdata# gpio23/dtr2# 1 gpio24/rts2# 2 gpio25/dsr2# 3 vcc 4 gpio26/sout2 5 gpio27/sin2 6 gpio30/densel# 7 gpio31/moa# 8 gpio32/drva# 9 gpio33/wdata# 10 gpio34/dir# 11 gpio35/step# 12 gpio36/hdsel# 13 gpio37/wgate# 14 gpio50/rdata# 15 gpio51/trk0# 16 gpio52/index# 17 gpio53/wpt# 18 gpio54/dskchg# 19 gnd 20 fanin1 21 fanctl1 22 fanin2 23 fanctl2 24 gpio40/fanin3 25 gpio41/fanctl3 26 gpio42/irtx 27 gpio43/irrx 28 lreset# 29 ldrq# 30 serirq 31 lfram# 32 lad0 33 lad1 34 lad2 35 lad3 36 vcc 37 pciclk 38 clkin 39 kbrst# 40 ga20 41 event_in# 42 ctrl0# 43 ctrl1# 44 5vsb 45 timi ng_3/ gpi o00 46 timi ng_4/ gpi o01 47 gnd 48 gpio63 49 gpio64 50 gpio65 51 ti mi n g_gpi o 52 timi ng_2/ gpi o02 53 timi ng_1/ gpi o03 54 st2/slotocc#/gpio04 55 st1/gpio05 56 peci_req#/tsi_clk/ibx_scl 57 peci/tsi_dat/ibx_sda 58 gpio10/pcirst4#/ibx_scl 59 gpio11/pcirst5#/ibx_sda 60 gpio12/rstcon#/fanctl_1 61 atx_pwrgdsw/gpio13/beep 62 wdtrst#/gpio14 63 gpio15/led_vsb/alert# 64 gpio16/led_vcc 65 cpu_pwrgd/gpio17 66 ovt# 67 vsb 68 kdata 69 kclk 70 mdata 71 mclk 72 gnd 73 pcirst1# 74 pcirst2# 75 pcirst3# 76 s5# 77 atxpg_in/gpio44 78 pme# 79 pwsin#/gpio45 80 pwsout#/gpio46 81 s3# 82 ps_on#/gpio47 83 pwok 84 rsmrst# 85 vbat 86 copen# 87 agnd(d-) 88 d3+(system) 89 d2+ 90 d+(cpu) 91 vref 92 vin6 93 vin5 94 vin4(vdimm) 95 vin3(vdda) 96 vin2(vldt) 97 vin1(vcore) 98 vsb 99 slct 100 pe 101 busy 102 ack# 103 slin# 104 init# 105 err# 106 afd# 107 stb# 108 pd0 109 pd1 110 pd2 111 pd3 112 pd4 113 pd5 114 pd6 115 pd7 116 gnd 117 dcd1# 118 ri1# 119 cts1# 120 dtr1#/fan40_100 121 rts1#/wdtrst# 122 dsr1# 123 sout1/config4e_2e 124 sin1 125 gpio20/dcd2# 126 gpio21/ri2# 127 gpio22/cts2# 128 F71869ED wdata#
finte k feature integration technology inc. dec, 2010 v0.21p 125 f71869e slct busy pe 1 2 3 4 5 6 7 8 rn5 33-8p4r 1 2 3 4 5 6 7 8 rn6 33-8p4r dsr2# rts2# dtr2# sin2 sout2 mc lk kdat kclk md at 1 2 3 4 5 6 7 8 rn2 2.7k-8p4r dcd1# dsr1# cts1# ri1# r17 4.7k if you do not use the uart port 1, please pull-up these pin to vcc3v. sin1 r19 4.7k r18 4.7k 1 2 3 4 5 6 7 8 rn4 2.7k-8p4r r21 4.7k r20 4.7k vcc3v 1 2 3 4 5 6 7 8 rn7 33-8p4r ring-in wake-up is supported by f71869. vcc5v/3v ri2# dcd2# if you do not use the uart port 2, please pull-up these pin to vcc3v. sin2 dsr2# cts2# r24 4.7k r23 4.7k r26 4.7k r25 4.7k r27 4.7k vcc3v 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 j2 db25 1 2 3 4 5 6 7 8 rn3 2.7k-8p4r 1 2 3 4 5 6 7 8 rn1 2.7k-8p4r cts1# ri1# dcd1# cts2# sout1 dsr1# rts1# dtr1# ri2# dcd2# sin1 vcc5v r22 2.7k c26 100p r28 4.7k r29 4.7k f1 fuse c27 0.1u l1 fb l3 fb c25 100p 1 2 3 4 5 6 js1 m-din_6-r r30 4.7k l2 fb if you do not use the kbc, please pull-up these pin to vsb5v. c28 100p 1 2 3 4 5 6 js2 m-din_6-r c30 0.1u c29 100p l4 fb f2 fuse 1 2 3 j3 con3 r31 4.7k ps2 keyboard interface ps2 mouse interface vsb5v rin2 -12v dtrn2 dsrn2 rtsn2 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u2 ctsn2 sinn2 gnd vcc5v soutn2 ctsn2 dcdn2 soutn2 dcdn2 sinn2 dsrn2 rtsn2 5 9 4 8 3 7 2 6 1 p2 uart db9 dtrn2 rin2 +12v 1 2 d1 1n5819 vcc5v pd7 ack# pd4 init# slin# pd6 pd5 pd0 stb# afd# err# pd3 pd2 pd1 tit le size document number rev date: sheet of printer &uart 0.11 feature integration technology inc. b 27 thursday , october 01, 2009 c15 180p c14 180p parallel port interface c16 180p for lekage to power c7 180p c17 180p (female) c8 180p c18 180p dtrn1 dsrn1 sinn1 ctsn1 gnd rtsn1 dcdn1 1 2 3 4 5 jp1 header 5 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u1 c9 180p soutn1 ctsn1 dsrn1 dtrn1 dcdn1 5 9 4 8 3 7 2 6 1 p1 uart db9 sinn1 c19 180p rtsn1 soutn1 c10 180p c20 180p uart 1 port interface c11 180p uart 2 port interface c21 180p c12 180p c22 180p c13 180p c24 0.1u rin1 rin1 ir interface c23 180p -12v +12v vcc5v irtx irrx
finte k feature integration technology inc. dec, 2010 v0.21p 126 f71869e q13 pnp 3906 for system c59 3300p d3+ diode sensing circuit d- d3 led d2 led r50 4.7k vcc3v ovt# pull-up ovt# r43 10k 1% d1+ vref t rt1 th er mi stor 10k 1% (for system) q1 pnp 3906 for system d1+ from cpu vref d2+ r46 10k 1% t rt2 th er mi stor 10k 1% (for system) thermistor sensing circuit d- d+ d- c32 3300p c33 3300p temperature sensing d2+ diode sensing circuit d- c31 100p c34 100p c38 100p c39 100p vdimm(vin4) r45 20k r47 2k r42 4.7k r35 10k r44 10k r34 10k r32 1k vldt(1.5v) vdimm vcore +12v voltage sensing. the best voltage input level is about 1v. vin6 vldt(vin2) vcore(vin1) c37 100p 5vsb r40 10k r38 10k vdda(vin3) title size document number rev date: sheet of hardware monitor 0.11 feature integration technology inc. b 37 thursday , october 01, 2009 r33 2m c35 1000p copen# vbat 1 2 sw1 case open circuit led_vsb sus_led vsb3v q3 npn vsb5v r49 4.7k r48 330 led p_led led_vcc vsb5v vsb3v r39 330 q2 npn r41 4.7k d3+ vref r114 10k 1% t rt3 th er mi stor 10k 1% thermistor sensing circuit (for system) 5vsb( for intel) c36 100p r37 10k r36 10k vdda vdda(vin3)
finte k feature integration technology inc. dec, 2010 v0.21p 127 f71869e fanctl2 r65 4.7k fanctl3 r78 4.7k fanctl3 vcc3v r51 4.7k vcc3v r63 4.7k r76 4.7k c47 0.1u r71 10k r70 27k r64 4.7k q6 pnp r62 4.7k r66 4.7k + c44 47u +12v 1 2 3 jp4 header 3 r69 330 q7 mosfet n 2n7002 d6 1n4148 c51 0.1u r83 10k fanctl1 r82 27k r77 4.7k q9 pnp r75 4.7k r79 4.7k + c48 47u +12v 1 2 3 jp6 header 3 r81 330 q10 mosfet n 2n7002 d8 1n4148 1 2 3 4 jp2 4 header vcc5v r53 4.7k r52 10k r55 27k r58 10k +12v + c40 47u d4 1n4148 c43 0.1u fanin1 r57 100 (4 pin fan control) fanctl1 tit le size document number rev date: sheet of fan control 0.11 feature integration technology inc. b 47 wednesday , september 30, 2009 pwm fan 3 speed control pwm fan 1 speed control pwm fan 2 speed control r61 3.9k r59 10k dc fan control with op 1 r72 10k 1 2 3 jp5 con3 fanin1 r74 3.9k r73 10k d7 1n4148 5 6 7 8 4 + - u3b lm358 dc fan control with op 2 r68 27k 12v r67 4.7k c45 47u q5 pmos c46 0.1u fanin2 12v q8 pmos r80 4.7k d9 1n4148 dc fan control with op 3 1 2 3 jp7 con3 12v c50 0.1u c49 47u r86 10k r85 10k r87 3.9k r84 27k 3 2 1 8 4 + - u4a lm358 fan control for pwm or dc fanin2 fanin3 q4 pmos fanin3 r56 27k 1 2 3 jp3 con3 r60 10k d5 1n4148 r54 4.7k c41 47u c42 0.1u 3 2 1 8 4 + - u3a lm358 fanctl2
finte k feature integration technology inc. dec, 2010 v0.21p 128 f71869e vcc3v vcc3v vsb3v power sequence pull-up client peci_client intel peci client r88 300 amd_tsi r89 300 vddio sid sic r92 100k 2.5v r97 4.7k cpu_pwrgd cpu_pwrgd pull-up peci ti mi ng_3 ti mi ng_2 timi ng_1 ti mi n g_4 r93 4.7k r94 4.7k r95 4.7k r96 4.7k peci_req# peci intel ibex client r91 300 r90 300 vcc3v ibx_clk ibx_dat (avoid pre-bios floating) smlink[1] title size document number rev date: sheet of amdsi/peci 0.11 feature integration technology inc. b 57 wednesday , september 30, 2009 vcc3v
finte k feature integration technology inc. dec, 2010 v0.21p 129 f71869e pson# pwsout# r102 1k pme# 5vsb_atx r101 10k r100 10k r99 10k 5vsb c54 10u c52 10u title size document number rev date: sheet of 0.11 b 67 wednesday , september 30, 2009 q11 mosfet p c53 1u 5vsb_atx ctrl0# r106 1k 5vsb_atx c57 10u 5vusb c55 10u q12 mosfet p c56 1u ctrl1# eup control vsb r105 10k r104 10k vsb3v event_in pwsin# eup acpi pull up r98 10k r103 10k <br> finte k feature integration technology inc. dec, 2010 v0.21p 130 f71869e 1 2 r110 33 -pwr_btn 2 1 c58 0.1uf rstgnd 5 reset 7 psw+ 6 psw- 8 front panel 1 2 r109 1 2 4.7k 3 4 4.7k vsb3 pcirst1# pcirst2# tit le size document number rev date: sheet of example_acpi 0.11 feature integration technology inc. a 77 wednesday , september 30, 2009 pson# pcirst3# rsmrst# atxpg_in pwsout# s3# pwsin# rstcon# pcirst1# pcirst2# 1 2 1k sata*2 pci front panel f71869 ata 133 ide atx connector south bridge cpu north bridge vcc3 pclk_1,2,3(33mhz) vsb5 1 2 r112 4.7k 1 2 tc 1 22uf 3v3 11 -12v 12 gnd 13 ps-on 14 gnd 15 gnd 16 gnd 17 -5v 18 5v 19 5v 20 3v3 1 3v3 2 gnd 3 5v 4 gnd 5 5v 6 gnd 7 pw-ok 8 5vsb 9 12v 10 atx1 atx connector vcc3 vcc5 vsb5 +12v vcc5 -12v 1 2 1k-8p4r vcc3 3 4 1k-8p4r vsb3 1 2 r107 4.7k vsb3 1 2 r113 4.7k vsb5 1 2 r108 4.7k lreset# <br></td> </tr> </table> <table border="0" width="980" id="table32" style="font-size:1px" height="10"> <tr> <td></td> </tr> </table> <table border="0" width="980" id="table31" style="font-size:1px" height="40"> <tr> <td background="images/bg03.gif"> <p align="right"><br> <font color="#FF0000"><a href="#top">▲Up To Search▲</a> </font></td> </tr> </table> <table border="0" width="980" id="table27"> <tr> <td> </td> </tr> <tr> <td> <b><font size="5">Price & Availability of F71869ED </font></b> <a target="_blank" href="https://www.findchips.com/search/F71869ED"><img border="0" src="images/fc_logo.jpg" width="265" height="25"></a></td> </tr> <tr> <td><script src="http://www.findchips.com/api/inventory/search/F71869ED?limit=5&partner=18"></script> <script>document.getElementById("poweredBy").style.visibility="hidden";</script></td> </tr> </table> </div> <div align="center"> <table border="0" width="980" id="table13" style="font-size:12px"> <tr> <td> <table border="0" width="980" id="table26" style="font-size:1px"> <tr> <td background="images/bg03.gif"></td> </tr> </table> </td> </tr> <tr> <td> <p align="right">All Rights Reserved © <span lang="zh-cn"> IC-ON-LINE 2003 - 2022</span> </td> </tr> </table> </div> <div align="center"> <table border="0" width="980" id="table13" style="font-size:12px"> <tr> <td>[<a href="javascript:addbookmark()">Add Bookmark</a>] [<a href="mailto:ioldatasheet@gmail.com" target="_blank">Contact Us</a>] [<a href="link.php">Link exchange</a>] [<a href="privacy.php">Privacy policy</a>]</td> </tr> <tr> <td> Mirror Sites : [<a href="http://www.datasheet.hk">www.datasheet.hk</a>] [<a href="http://www.maxim4u.com">www.maxim4u.com</a>] [<a href="http://www.ic-on-line.cn">www.ic-on-line.cn</a>] [<a href="http://www.ic-on-line.com">www.ic-on-line.com</a>] [<a href="http://www.ic-on-line.net">www.ic-on-line.net</a>] [<a href="http://www.alldatasheet.com.cn">www.alldatasheet.com.cn</a>] [<a href="http://www.gdcy.com">www.gdcy.com</a>] [<a href="http://www.gdcy.net">www.gdcy.net</a>]<br><br><br></td> </tr> </table> </div> <style type="text/css"> .style1 { background-color: #333333; } .style2 { color: #FFFFFF; } .style3 { color: #0000FF; } .style4 { color: #FFFFFF; font-size: large; } .style5 { text-decoration: none; } .style6 { color: #6EF3F2; } .style7 { border-width: 0px; } </style> <a href="http://www.maxim4u.com/che_s1.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s2.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s3.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s4.php" rel="nofollow">.</a> <a href="http://www.maxim4u.com/che_s5.php" rel="nofollow">.</a> <br> <div style="position:fixed ;bottom:0px;width:100%" id="id_cookies"> <table height="33" align="center" class="style1" style="width: 100%"> <tr> <td align="left" class="style2" style="width: 23px"> </td> <td align="left" class="style2">We use cookies to deliver the best possible web experience and assist with our advertising efforts. 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